I²C signal rise times are dictated by the bus pull-up resistors which are sometimes inadequate if a faster slewing bus is desired. This is the case in PICMG specifications, which call for both the SCL and SDA signals to rise from 1V to 2.3V in 900ns with a 2.7kΩ pull-up to 3.3V and a 690pF load. This is why Analog Devices offers many bus buffers with selectable rise time acceleration, as well as stand-alone dedicated rise time accelerators that hang off the bus as shown here. These autonomous rise time accelerators provide strong, slew-limited pull-up currents so that rise time requirements are met. The accelerators are automatically activated during positive bus transitions and make the bus voltages rise at a particular rate. This improves board and system reliability by providing smooth, controlled transitions during rising edges. Systems also become less susceptible to noise on rising edges since the accelerator pull-ups present impedances lower than bus pull-up resistances. Additionally, the accelerators permit the use of larger bus pull-ups. This reduces power consumption and improves the logic low-noise margin.