Phase noise specs are generally provided for applications or devices having stringent jitter requirements. Phase noise is a measurement of jitter in the frequency domain. Explaining phase noise is out of the scope of this presentation, but as a general rule, the lower the phase noise, the lower the clock jitter. If a chipset manufacturer specifies phase noise values, the compliance of the clock generator is tested by comparing the requirement to a phase noise plot of the clock generator. Phase noise plots are generally found in the datasheet of the devices. Be sure to consider a phase noise plot measured at the same frequency as the desired clock. In some cases, such as programmable clock generators capable of generating virtually any frequency, it is not practical to include a series of phase noise plots in the datasheet. As a service to customers, Renesas will measure phase noise of clock generators under conditions required by a specific application. As an example, the LS1043A chipset requires a phase noise of less than -56 dBc per Hertz at 100 MHz clock. The designer considers the programmable VersaClock 6 to clock the chipset. Is it suitable?