Paramètres
Livraison rapide
Livraison gratuite
Incoterms
Types de paiement
Produit marketplace
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Product List
Looking at the block diagram for the L6506 you see two fixed frequency PWM circuits plus the logic to combine the PWM signal with the phase information from the step generator and then feed that to the two power bridges. The peak motor current is regulated by sensing the voltage across the resistor on the Vsense inputs and comparing it to the reference input. When the voltage at the Vsense input reaches the reference voltage, the comparator will reset flip-flop that will cause the PWM to turn the bridge off. The oscillator sets the flip-flop at a fixed frequency and the cycle repeats. Generally the L6506 is connected to the phase inputs of the power bridge so it typically implements phase chopping or slow decay mode chopping in the bridge.
PTM Published on: 2011-12-14
France