A common trade-off for improving ON-state resistance of a MOSFET is a compromise in short-circuit ruggedness. When a power MOSFET is designed with lower conduction loss, its saturation current level at high drain voltages tends to increase as a result. The 4^th Generation SiC MOSFET does not achieve its low specific ON-resistance by sacrificing the short-circuit withstand time. The saturation current is suppressed by chip design, despite a steeper slope in the current-voltage relationship for the conduction state. By optimizing performance for both the ON-state and short-circuit conditions, the conventional trade-off relationship is improved, giving the 4^th Generation devices a significant advantage in achieving high efficiency and robust short-circuit ruggedness at the same time.