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ANALOG L POWER EY DEVICES ‘ D LINEAR“ LT3042

LT3042

3042fb

For more information www.linear.com/LT3042

TYPICAL APPLICATION

FEATURES DESCRIPTION

20V, 200mA, Ultralow Noise,

Ultrahigh PSRR RF Linear Regulator

The LT

3042 is a high performance low dropout linear

regulator featuring LTC’s ultralow noise and ultrahigh PSRR

architecture for powering noise sensitive RF applications.

Designed as a precision current reference followed by a

high performance voltage buffer, the LT3042 can be easily

paralleled to further reduce noise, increase output current

and spread heat on the PCB.

The device supplies 200mA at a typical 350mV dropout

voltage. Operating quiescent current is nominally 2mA

and drops to <<1µA in shutdown. The LT3042’s wide

output voltage range (0V to 15V) while maintaining unity-

gain operation provides virtually constant output noise,

PSRR, bandwidth and load regulation, independent of the

programmed output voltage. Additionally, the regulator

features programmable current limit, fast start-up capa-

bility and programmable power good to indicate output

voltage regulation.

The LT3042 is stable with a minimum 4.7µF ceramic

output capacitor. Built-in protection includes reverse bat-

tery protection, reverse current protection, internal current

limit with foldback and thermal limit with hysteresis. The

LT3042 is available in thermally enhanced 10-Lead MSOP

and 3mm × 3mm DFN packages.

Power Supply Ripple Rejection

APPLICATIONS

n Ultralow RMS Noise: 0.8µVRMS (10Hz to 100kHz)

n Ultralow Spot Noise: 2nV/√Hz at 10kHz

n Ultrahigh PSRR: 79dB at 1MHz

n Output Current: 200mA

n Wide Input Voltage Range: 1.8V to 20V

n Single Capacitor Improves Noise and PSRR

n 100µA SET Pin Current: ±1% Initial Accuracy

n Single Resistor Programs Output Voltage

n High Bandwidth: 1MHz

n Programmable Current Limit

n Low Dropout Voltage: 350mV

n Output Voltage Range: 0V to 15V

n Programmable Power Good

n Fast Start-Up Capability

n Precision Enable/UVLO

n Parallelable for Lower Noise and Higher Current

n Internal Current Limit with Foldback

n Minimum Output Capacitor: 4.7µF Ceramic

n Reverse Battery and Reverse Current Protection

n 10-Lead MSOP and 3mm × 3mm DFN Packages

n RF Power Supplies: PLLs, VCOs, Mixers, LNAs

n Very Low Noise Instrumentation

n High Speed/High Precision Data Converters

n Medical Applications: Imaging, Diagnostics

n Precision Power Supplies

n Post-Regulator for Switching Supplies

All registered trademarks and trademarks are the property of their respective owners. Patents

Pending.

FREQUENCY (Hz)

PSRR (dB)

120

100

10 100 10k 100k 1M 10M

3042 TA01b

20 1k

110

VIN = 5V

RSET = 33.2kΩ

CSET = 4.7µF

COUT = 4.7µF

IL = 200mA

–

100µA

EN/UV

GND

OUT

LT3042

ILIM PGFB 453k

4.7µF

VIN

5V ±5%

200k

4.7µF

VOUT

3.3V

OUT(MAX)

200mA

49.9k

3042 TA01a

499Ω

33.2k

SET

OUTS

LT3042 TOP VIEW TOP vwEw ﬂﬂﬂﬂﬂ DE IL L MSE PACKAGE mrLEAD PLAS'HC MSUP

LT3042

3042fb

For more information www.linear.com/LT3042

PIN CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

IN Pin Voltage .........................................................±22V

EN/UV Pin Voltage ..................................................±22V

IN-to-EN/UV Differential..........................................±22V

PG Pin Voltage (Note 10) ...............................–0.3V, 22V

ILIM Pin Voltage (Note 10) ............................... –0.3V, 1V

PGFB Pin Voltage (Note 10) ...........................–0.3V, 22V

SET Pin Voltage (Note 10) ..............................–0.3V, 16V

SET Pin Current (Note 7) .................................... ±20mA

OUTS Pin Voltage (Note 10) ........................... –0.3V, 16V

OUTS Pin Current (Note 7) ................................. ±20mA

OUT Pin Voltage (Note 10) .............................–0.3V, 16V

(Note 1)

TOP VIEW

GND

DD PACKAGE

10-LEAD (3mm

3mm) PLASTIC DFN

1OUT

OUTS

GND

SET

PGFB

EN/UV

ILIM

TJMAX = 150°C, θJA = 34°C/W, θJC = 5.5°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

EN/UV

ILIM

OUT

OUTS

GND

SET

PGFB

TOP VIEW

GND

MSE PACKAGE

10-LEAD PLASTIC MSOP

TJMAX = 150°C, θJA = 33°C/W, θJC = 8°C/W

EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT3042EDD#PBF LT3042EDD#TRPBF LGSJ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT3042IDD#PBF LT3042IDD#TRPBF LGSJ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT3042HDD#PBF LT3042HDD#TRPBF LGSJ 10-Lead (3mm × 3mm) Plastic DFN –40°C to 150°C

LT3042MPDD#PBF LT3042MPDD#TRPBF LGSJ 10-Lead (3mm × 3mm) Plastic DFN –55°C to 150°C

LT3042EMSE#PBF LT3042EMSE#TRPBF LTGSH 10-Lead Plastic MSOP –40°C to 125°C

LT3042IMSE#PBF LT3042IMSE#TRPBF LTGSH 10-Lead Plastic MSOP –40°C to 125°C

LT3042HMSE#PBF LT3042HMSE#TRPBF LTGSH 10-Lead Plastic MSOP –40°C to 150°C

LT3042MPMSE#PBF LT3042MPMSE#TRPBF LTGSH 10-Lead Plastic MSOP –55°C to 150°C

Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult ADI Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through

designated sales channels with #TRMPBF suffix.

OUT-to-OUTS Differential (Note 14) ....................... ±1.2V

IN-to-OUT Differential .............................................±22V

IN-to-OUTS Differential ........................................... ±22V

Output Short-Circuit Duration .......................... Indefinite

Operating Junction Temperature Range (Note 9)

E-, I-Grade ........................................ –40°C to 125°C

H-Grade ............................................ –40°C to 150°C

MP-Grade ......................................... –55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

Lead Temperature (Soldering, 10 Sec)

MSE Package ...................................................300°C

http://www.linear.com/product/LT3042#orderinfo

LT3042

3042fb

For more information www.linear.com/LT3042

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Minimum IN Pin Voltage

(Note 2)

ILOAD = 200mA, VIN UVLO Rising

VIN UVLO Hysteresis

l1.78

2 V

SET Pin Current (ISET) VIN = 2V, ILOAD = 1mA, VOUT = 1.3V

2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA (Note 3)

100

101

102

µA

Fast Start-Up Set Pin

Current

VPGFB = 289mV, VIN = 2.8V, VSET = 1.3V 2 mA

Output Offset Voltage

VOS (VOUT – VSET)

(Note 4)

VIN = 2V, ILOAD = 1mA, VOUT = 1.3V

2V < VIN < 20V, 0V < VOUT < 15V, 1mA < ILOAD < 200mA (Note 3)

–1

–2

Line Regulation: ∆ISET

Line Regulation: ∆VOS

VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V

VIN = 2V to 20V, ILOAD = 1mA, VOUT = 1.3V (Note 4)

0.5

±2

±3

nA/V

µV/V

Load Regulation: ∆ISET

Load Regulation: ∆VOS

ILOAD = 1mA to 200mA, VIN = 2V, VOUT = 1.3V

ILOAD = 1mA to 200mA, VIN = 2V, VOUT = 1.3V (Note 4)

0.1

0.5

Change in ISET with VSET

Change in VOS with VSET

Change in ISET with VSET

Change in VOS with VSET

VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA

VSET = 1.3V to 15V, VIN = 20V, ILOAD = 1mA (Note 4)

VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA

VSET = 0V to 1.3V, VIN = 20V, ILOAD = 1mA (Note 4)

0.03

150

0.3

400

0.6

600

Dropout Voltage ILOAD = 1mA, 50mA

220 270

300

ILOAD = 150mA (Note 5) 270 mV

ILOAD = 200mA (Note 5) 350 mV

GND Pin Current

VIN = VOUT(NOMINAL)

(Note 6)

ILOAD = 10µA

ILOAD = 1mA

ILOAD = 50mA

ILOAD = 100mA

ILOAD = 200mA

1.9

3.2

4.5

7.6

3.5

Output Noise Spectral

Density (Notes 4, 8)

ILOAD = 200mA, Frequency = 10Hz, COUT = 4.7µF, CSET = 0.47µF, VOUT = 3.3V

ILOAD = 200mA, Frequency = 10Hz, COUT = 4.7µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V

ILOAD = 200mA, Frequency = 10kHz, COUT = 4.7µF, CSET = 0.47µF, 1.3V ≤ VOUT ≤ 15V

ILOAD = 200mA, Frequency = 10kHz, COUT = 4.7µF, CSET = 0.47µF, 0V ≤ VOUT < 1.3V

300

nV/√Hz

Output RMS Noise

(Notes 4, 8)

ILOAD = 200mA, BW = 10Hz to 100kHz, COUT = 4.7µF, CSET = 0.47µF, VOUT = 3.3V

ILOAD = 200mA, BW = 10Hz to 100kHz, COUT = 4.7µF, CSET = 4.7µF, 1.3V ≤ VOUT ≤ 15V

ILOAD = 200mA, BW = 10Hz to 100kHz, COUT = 4.7µF, CSET = 4.7µF, 0V ≤ VOUT < 1.3V

1.9

0.8

1.6

µVRMS

Reference Current RMS

Output Noise (Notes 4, 8)

BW = 10Hz to 100kHz 6 nARMS

Ripple Rejection

1.3V ≤ VOUT ≤ 15V

VIN – VOUT = 2V (Avg)

(Notes 4, 15)

VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 200mA, COUT = 4.7µF, CSET = 4.7µF

VRIPPLE = 150mVP-P, fRIPPLE = 10kHz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

VRIPPLE = 150mVP-P, fRIPPLE = 100kHz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

VRIPPLE = 150mVP-P, fRIPPLE = 1MHz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

VRIPPLE = 80mVP-P, fRIPPLE = 10MHz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

95 117

Ripple Rejection

0V ≤ VOUT < 1.3V

VIN – VOUT = 2V (Avg)

(Notes 4, 8)

VRIPPLE = 500mVP-P, fRIPPLE = 120Hz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

VRIPPLE = 50mVP-P, fRIPPLE = 10kHz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

VRIPPLE = 50mVP-P, fRIPPLE = 100kHz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

VRIPPLE = 50mVP-P, fRIPPLE = 1MHz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

VRIPPLE = 50mVP-P, fRIPPLE = 10MHz, ILOAD = 200mA, COUT = 4.7µF, CSET = 0.47µF

104

EN/UV Pin Threshold EN/UV Trip Point Rising (Turn-On), VIN = 2V l1.18 1.24 1.32 V

EN/UV Pin Hysteresis EN/UV Trip Point Hysteresis, VIN = 2V 170 mV

EN/UV Pin Current VEN/UV = 0V, VIN = 20V

VEN/UV = 1.24V, VIN = 20V

VEN/UV = 20V, VIN = 0V

0.2

±1

µA

LT3042

3042fb

For more information www.linear.com/LT3042

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Quiescent Current in

Shutdown (VEN/UV = 0V)

VIN = 6V

0.3 1

µA

Internal Current Limit

(Note 12)

VIN = 2V, VOUT = 0V

VIN = 12V, VOUT = 0V

VIN = 20V, VOUT = 0V

220

130

270

300

180

320

250

Programmable

Current Limit

Programming Scale Factor: 2V< VIN < 20V (Note 11)

VIN = 2V, VOUT = 0V, RILIM = 625Ω

VIN = 2V, VOUT = 0V, RILIM = 2.5kΩ

180

125

200

220

mA • kΩ

PGFB Trip Point PGFB Trip Point Rising l291 300 309 mV

PGFB Hysteresis PGFB Trip Point Hysteresis 7 mV

PGFB Pin Current VIN = 2V, VPGFB = 300mV 25 nA

PG Output Low Voltage IPG = 100µA l30 100 mV

PG Leakage Current VPG = 20V l1 µA

Reverse Input Current VIN = –20V, VEN/UV = 0V, VOUT = 0V, VSET = 0V l50 µA

Reverse Output Current VIN = 0, VOUT = 5V, SET = Open 2 5 µA

Minimum Load Required

(Note 13)

VOUT < 1V l10 µA

Thermal Shutdown TJ Rising

Hysteresis

162

°C

Start-Up Time VOUT(NOM) = 5V, ILOAD = 200mA, CSET = 0.47µF, VIN = 6V, VPGFB = 6V

VOUT(NOM) = 5V, ILOAD = 200mA, CSET = 4.7µF, VIN = 6V, VPGFB = 6V

VOUT(NOM) = 5V, ILOAD = 200mA, CSET = 4.7µF, VIN = 6V, RPG1 = 50kΩ,

RPG2 = 700kΩ (with Fast Start-Up to 90% of VOUT)

550

Thermal Regulation 10ms Pulse –0.01 %/W

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The EN/UV pin threshold must be met to ensure device operation.

Note 3: Maximum junction temperature limits operating conditions. The

regulated output voltage specification does not apply for all possible

combinations of input voltage and output current, especially due to the

internal current limit foldback which starts to decrease current limit at

VIN – VOUT > 12V. If operating at maximum output current, limit the input

voltage range. If operating at the maximum input voltage, limit the output

current range.

Note 4: OUTS ties directly to OUT.

Note 5: Dropout voltage is the minimum input-to-output differential

voltage needed to maintain regulation at a specified output current. The

dropout voltage is measured when output is 1% out of regulation. This

definition results in a higher dropout voltage compared to hard dropout —

which is measured when VIN = VOUT(NOMINAL). For lower output voltages,

below 1.5V, dropout voltage is limited by the minimum input voltage

specification. Linear Technology is unable to guarantee maximum

dropout voltage specifications at high currents due to production test

limitations with Kelvin-sensing the package pins. Please consult the

Typical Performance Characteristics for curves of dropout voltage as a

function of output load current and temperature measured in a typical

application circuit.

Note 6: GND pin current is tested with VIN = VOUT(NOMINAL) and a current

source load. Therefore, the device is tested while operating in dropout.

This is the worst-case GND pin current. GND pin current decreases at

higher input voltages. Note that GND pin current does not include SET pin

or ILIM pin current but Quiescent current does include them.

Note 7: SET and OUTS pins are clamped using diodes and two 25Ω series

resistors. For less than 5ms transients, this clamp circuitry can carry

more than the rated current. Refer to Applications Information for more

information.

Note 8: Adding a capacitor across the SET pin resistor decreases output

voltage noise. Adding this capacitor bypasses the SET pin resistor’s

thermal noise as well as the reference current’s noise. The output noise

then equals the error amplifier noise. Use of a SET pin bypass capacitor

also increases start-up time.

Note 9: The LT3042 is tested and specified under pulsed load conditions

such that TJ ≈ TA. The LT3042E is 100% tested at 25°C and performance

is guaranteed from 0°C to 125°C. Specifications over the –40°C to 125°C

operating temperature range are assured by design, characterization, and

correlation with statistical process controls. The LT3042I is guaranteed

over the full –40°C to 125°C operating temperature range. The LT3042MP

is 100% tested and guaranteed over the full –55°C to 150°C operating

temperature range. The LT3042H is 100% tested at the 150°C operating

junction temperature. High junction temperatures degrade operating

lifetimes. Operating lifetime is derated at junction temperatures greater

than 125°C.

LT3042 Es WEEEEEE um] 23%118 25 mm Es 5%?sz um] 23 Egg 25 mm A ‘ 354

LT3042

3042fb

For more information www.linear.com/LT3042

TYPICAL PERFORMANCE CHARACTERISTICS

Offset Voltage SET Pin Current Offset Voltage (VOUT – VSET)

SET Pin Current SET Pin Current Offset Voltage (VOUT – VSET)

TJ = 25°C, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Note 10: Parasitic diodes exist internally between the ILIM, PG, PGFB, SET,

OUTS, and OUT pins and the GND pin. Do not drive these pins more than

0.3V below the GND pin during a fault condition. These pins must remain

at a voltage more positive than GND during normal operation.

Note 11: The current limit programming scale factor is specified while the

internal backup current limit is not active. Note that the internal current

limit has foldback protection for VIN – VOUT differentials greater than 12V.

Note 12: The internal back-up current limit circuitry incorporates foldback

protection that decreases current limit for VIN – VOUT > 12V. Some level of

output current is provided at all VIN – VOUT differential voltages. Consult

the Typical Performance Characteristics graph for current limit vs VIN –

VOUT.

Note 13: For output voltages less than 1V, the LT3042 requires a 10µA

minimum load current for stability.

Note 14: Maximum OUT-to-OUTS differential is guaranteed by design.

Note 15: The PSRR at 120Hz is guaranteed by design, characterization,

and correlation with statistical process controls.

TEMPERATURE (°C)

–75

SET PIN CURRENT (µA)

101.0

99.2

100.8

100.4

100.0

99.6

100.6

100.2

99.8

99.4

99.0 25 125–25 75

3042 G01

150

0 100–50 50

VIN = 2V

IL = 1mA

VOUT = 1.3V

TEMPERATURE (°C)

–75

OFFSET VOLTAGE (mV)

2.0

1.5

0.5

–0.5

–1.5

1.0

–1.0

–2.0 25 125–25 75

3042 G03

150

0 100–50 50

VIN = 2V

IL = 1mA

VOUT = 1.3V

ISET DISTRIBUTION (µA)

10199

3042 G02

102

100

N = 4354

VOS DISTRIBUTION (mV)

–2

1–1

3042 G04

N = 4354

SET PIN CURRENT (µA)

101.0

99.2

100.8

100.4

100.0

99.6

100.6

100.2

99.8

99.4

99.0

INPUT VOLTAGE (V)

0 10 186 14

3042 G05

8 164 122

IL = 1mA

VOUT = 1.3V

150°C

125°C

25°C

–55°C

INPUT VOLTAGE (V)

OFFSET VOLTAGE (mV)

2.0

–1.5

1.5

0.5

–0.5

1.0

–1.0

–2.0 10 186 14

3042 G06

8 164 122

IL = 1mA

VOUT = 1.3V

150°C

125°C

25°C

–55°C

LT3042 < 65="" 88:52.="" 35="" 25="" sun="" 2722:2323="" e823="" 3535553133="" 25="" 3.2.58!="" 23="" _="" 500="" 23:22:23="" e823="" :15="" 845359513="" $5="" 85358qu="" ”="" .-="" _="" _="" .="" n2="" _="" _="" _="" .="" mm="" 30="" 35="" 2722:2323="" e823="" 27522328="" e823="" 6="" 232e223="" 23="" mm="">

LT3042

3042fb

For more information www.linear.com/LT3042

TYPICAL PERFORMANCE CHARACTERISTICS

Quiescent Current Typical Dropout Voltage Dropout Voltage

Quiescent Current Quiescent Current in Shutdown Quiescent Current

TJ = 25°C, unless otherwise noted.

SET Pin Current Offset Voltage (VOUT – VSET) Load Regulation

SET PIN CURRENT (µA)

101.0

99.2

100.8

100.4

100.0

99.6

100.6

100.2

99.8

99.4

99.0

OUTPUT VOLTAGE (V)

0 7.5 13.54.5 10.5

3042 G07

6 123 91.5

IL = 1mA

VIN = 20V

150°C

125°C

25°C

–55°C

TEMPERATURE (°C)

–75

QUIESCENT CURRENT (mA)

3.0

2.5

1.5

0.5

2.0

1.0

025 125–25 75

3042 G10

150

0 100–50 50

VIN = 2V

VEN/UV = VIN

IL = 10µA

RSET = 13kΩ

OUTPUT VOLTAGE (V)

QUIESCENT CURRENT (mA)

3.5

2.5

2.0

3.0

1.5

0.5

1.0

0106 14

3042 G13

84 122

VIN = 20V

VEN/UV = VIN

IL = 10µA

150°C

125°C

25°C

–55°C

DROPOUT VOLTAGE (mV)

500

450

350

250

150

400

300

200

100

OUTPUT CURRENT (mA)

0 75 17525 125

3042 G14

200

50 150100

RSET = 33.2kΩ

150°C

125°C

25°C

–55°C

DROPOUT VOLTAGE (mV)

500

450

350

250

150

400

300

200

100

3042 G15

RSET = 33.2kΩ

IL = 200mA

IL = 150mA

IL = 100mA

IL = 1mA

TEMPERATURE (°C)

–75 25 125–25 75 1500 100–50 50

TEMPERATURE (°C)

–75

QUIESCENT CURRENT (µA)

25 125–25 75

3042 G11

150

0 100–50 50

VEN/UV = 0V

VIN = 2V

VIN = 20V

INPUT VOLTAGE (V)

QUIESCENT CURRENT (mA)

2.5

2.0

1.5

0.5

1.0

010 186 14

3042 G12

8 164 122

IL = 10µA

RSET = 33.2kΩ

OFFSET VOLTAGE (mV)

2.0

–1.5

1.5

0.5

–0.5

1.0

–1.0

–2.0

OUTPUT VOLTAGE (V)

0 7.5 13.54.5 10.5

3042 G08

6 123 91.5

IL = 1mA

VIN = 20V

150°C

125°C

25°C

–55°C

TEMPERATURE (°C)

–75

SET

LOAD REGULATION (nA)

LOAD REGULATION (mV)

0.20

0.02

0.18

0.14

0.10

0.06

0.16

0.12

0.08

0.04

25 125–25 75

3042 G09

1500 100–50 50

VIN = 2.5V

∆IL = 1mA TO 200mA

VOUT = 1.3V

VOS

ISET

LT3042 is FEES 23 a; 2.5 :35; 2.1 25 2:: 5:18 25 o5 vwauv 25a ‘32 200 mswe UVLO E5 235%): 2; >25 235118 2: >95 23:955 25 23$ E 39%;: .5.sz FALUNG uvm SEOIEESE 5%. 235118 2: >95

LT3042

3042fb

For more information www.linear.com/LT3042

TYPICAL PERFORMANCE CHARACTERISTICS

Enable Pin Input Current Enable Pin Current Negative Enable Pin Current

GND Pin Current GND Pin Current GND Pin Current

Minimum Input Voltage EN/UV Turn-On Threshold EN/UV Pin Hysteresis

TJ = 25°C, unless otherwise noted.

GND PIN CURRENT (mA)

3042 G16

VIN = 5V

RSET = 33.2kΩ

IL = 200mA

IL = 150mA

IL = 100mA

IL = 1mA

TEMPERATURE (°C)

–75 25 125–25 75

150

0 100–50 50

TEMPERATURE (°C)

–75

INPUT UVLO THRESHOLD (V)

2.00

1.75

1.25

0.75

0.25

1.50

1.00

0.50

025 125–25 75

3042 G19

150

0 100–50 50

RISING UVLO

FALLING UVLO

ENABLE PIN VOLTAGE (V)

EN/UV PIN CURRENT (µA)

10 186 14

3042 G22

8 164 122

VIN = 20V

5.0

0.5

4.5

3.5

2.5

1.5

4.0

3.0

2.0

1.0

150°C

125°C

25°C

–55°C

ENABLE PIN VOLTAGE (V)

EN/UV PIN CURRENT (µA)

10 186 14

3042 G23

8 164 122

VIN = 20V

VIN = 2V

ENABLE PIN VOLTAGE (V)

–20

EN/UV PIN CURRENT (µA)

–10 –2–14 –6

3042 G24

–12 –4–16 –8–18

VIN = 2V

–90

–10

–30

–50

–70

–20

–40

–60

–80

–100

150°C

125°C

25°C

–55°C

TEMPERATURE (°C)

–75

TURN-ON THRESHOLD (V)

1.32

1.30

1.26

1.22

1.28

1.24

1.20

1.18 25 125–25 75

3042 G20

150

0 100–50 50

VIN = 2V

VIN = 10V

TEMPERATURE (°C)

–75

EN/UV PIN HYSTERESIS (mV)

250

225

175

125

200

150

100 25 125–25 75

3042 G21

150

0 100–50 50

VIN = 2V

VIN = 10V

GND PIN CURRENT (mA)

OUTPUT CURRENT (mA)

0 75 17525 125

3042 G17

200

50 150100

VIN = 4.3V

RSET = 33.2kΩ

INPUT VOLTAGE (V)

GND PIN CURRENT (mA)

05 93 7

3042 G18

4 82 61

RSET = 33.2kΩ

RL = 16.5Ω

RL = 3.3kΩ

RL = 33Ω

RL = 66Ω

RL = 330Ω

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TYPICAL PERFORMANCE CHARACTERISTICS

ILIM Pin Current PGFB Rising Threshold PGFB Hysteresis

Internal Current Limit Programmable Current Limit Programmable Current Limit

TJ = 25°C, unless otherwise noted.

Input Pin Current Internal Current Limit Internal Current Limit

ENABLE PIN VOLTAGE (V)

–20

INPUT CURRENT (mA)

–10 –2–14 –6

3042 G25

–12 –4–16 –8–18

VIN = 2V

0.3

0.1

0.2

150°C

125°C

25°C

–55°C

0 10 186 14

8 164 122

CURRENT LIMIT (mA)

500

450

350

250

150

400

300

200

100

3042 G28

RILIM = 0Ω

150°C

125°C

25°C

–55°C

INPUT-TO-OUTPUT DIFFERENTIAL (V)

START OF FOLDBACK

0 100 18060 140

200

80 16040 12020

ILIM PIN CURRENT (µA)

500

450

350

250

150

400

300

200

100

3042 G31

VILIM = 0V

RSET = 33.2kΩ

OUTPUT CURRENT (mA)

VIN = 2.5V

VIN = 5V

VIN = 10V

CURRENT LIMIT (mA)

500

450

350

250

150

400

300

200

100

3042 G26

RILIM = 0Ω

VOUT = 0V

VIN = 7.5V

VIN = 2.5V

TEMPERATURE (°C)

–75 25 125–25 75

150

0 100–50 50

CURRENT LIMIT (mA)

400

350

250

150

300

200

100

3042 G29

RILIM = 625Ω

VOUT = 0V

VIN = 7.5V

VIN = 2.5V

TEMPERATURE (°C)

–75 25 125–25 75

150

0 100–50 50

PGFB RISING THRESHOLD (mV)

310

292

308

304

300

296

306

302

298

294

290

3042 G32

VIN = 2V

TEMPERATURE (°C)

–75 25 125–25 75

150

0 100–50 50

CURRENT LIMIT (mA)

300

250

150

200

100

3042 G27

VIN = 20V

RILIM = 0Ω

VOUT = 0V

TEMPERATURE (°C)

–75 25 125–25 75 1500 100–50 50

CURRENT LIMIT (mA)

100

3042 G30

RILIM = 2.49kΩ

VOUT = 0V

VIN = 7.5V

VIN = 2.5V

TEMPERATURE (°C)

–75 25 125–25 75 1500 100–50 50

PGFB HYSTERESIS (mV)

3042 G33

VIN = 2V

TEMPERATURE (°C)

–75 25 125–25 75 1500 100–50 50

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LT3042

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TYPICAL PERFORMANCE CHARACTERISTICS

VOUT Forced Above VOUT(NOMINAL) Power Supply Ripple Rejection Power Supply Ripple Rejection

PG Output Low Voltage PG Pin Leakage Current

ISET During Start-Up with Fast

Start-Up Enabled

ISET During Start-Up with Fast

Start-Up Enabled

Output Overshoot Recovery

Current Sink

Output Overshoot Recovery

Current Sink

TJ = 25°C, unless otherwise noted.

(mV)

3042 G34

VIN = 2V

VPGFB = 290mV

IPG = 100µA

TEMPERATURE (°C)

–75 25 125–25 75

150

0 100–50 50

CURRENT (mA)

3042 G40

OUTPUT VOLTAGE (V)

4 10 148 12

9 1375 6 11

VIN = 5V

RSET = 33.2kΩ

OUTPUT CURRENT

INPUT CURRENT

VOUT – VSET (mV)

OUTPUT SINK CURRENT (mA)

05 15

3042 G38

VIN = 5V

RSET = 33.2kΩ

155°C

130°C

25°C

–55°C

PSRR (dB)

120

110

100

3042 G41

FREQUENCY (Hz)

10 100 1k 1M

10M

100k10k

VIN = 5V

RSET = 33.2kΩ

COUT = 4.7µF

IL = 200mA

CSET = 4.7µF

CSET = 0.47µF

OUTPUT SINK CURRENT (mA)

3042 G39

TEMPERATURE (°C)

–75 25 125–25 75

150

0 100–50 50

VIN = 5V

RSET = 33.2kΩ

VOUT – VSET > 5mV

PSRR (dB)

120

110

100

3042 G42

FREQUENCY (Hz)

10 100 1k 1M

10M

100k10k

VIN = 5V

RSET = 33.2kΩ

CSET = 0.47µF

IL = 200mA

COUT = 4.7µF

COUT = 22µF

(nA)

100

3042 G35

VPG = 2V

VPGFB = 310mV

TEMPERATURE (°C)

–75 25 125–25 75

150

0 100–50 50

SET

(mA)

2.5

2.0

1.0

1.5

0.5

3042 G36

TEMPERATURE (°C)

–75 25 125–25 75 1500 100–50 50

VIN = 2.5V

VPGFB = 290mV

VSET = 1.3V

PGFB

= 290mV

SET

= 1.3V

-TO-V

SET

DIFFERENTIAL (V)

0.5

1.0

1.5

2.0

2.5

3.0

3.5

SET

(mA)

3042 G37

LT3042 mu um 55%,; gig ma: 5&3 120 mu 33 EE 3 >3 ma: 5&3 ms; €22: wmaz 5&8 ‘20 mm 0 1 5511mm 3 >3 wmaz 5:8 Em 313323515.“

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TYPICAL PERFORMANCE CHARACTERISTICS

Integrated RMS Output Noise

(10Hz to 100kHz)

Noise Spectral Density

Integrated RMS Output Noise

(10Hz to 100kHz)

Noise Spectral Density

Integrated RMS Output Noise

(10Hz to 100kHz)

Noise Spectral Density

TJ = 25°C, unless otherwise noted.

Power Supply Ripple Rejection

as a Function of Error Amplifier

Input Pair Power Supply Ripple Rejection

PSRR (dB)

120

110

100

3042 G43

FREQUENCY (Hz)

10 100 1k 1M

10M

100k10k

VIN = 5V

RSET = 33.2kΩ

COUT = 4.7µF

CSET = 0.47µF

IL = 200mA

IL = 100mA

IL = 50mA

IL = 1mA

0 100 18060 140

200

80 16040 12020

RMS OUTPUT NOISE (µV

RMS

)

2.0

0.2

1.8

1.4

1.0

0.6

1.6

1.2

0.8

0.4

3042 G46

LOAD CURRENT (mA)

VIN = 5V

RSET = 33.2kΩ

COUT = 4.7µF

CSET = 4.7µF

OUTPUT NOISE (nV/√Hz)

100

0.1

3042 G50

FREQUENCY (Hz)

10 100 1k 1M

10M

100k10k

VIN = 5V

RSET = 33.2kΩ

CSET = 4.7µF

IL = 200mA

COUT = 4.7µF

COUT = 22µF

PSRR (dB)

120

110

100

3042 G44

FREQUENCY (Hz)

10 100 1k 1M

10M

100k10k

VIN = VOUT + 2V

IL = 200mA

COUT = 4.7µF

CSET = 0.47µF

VOUT ≥ 1.3V

0.6V < VOUT < 1.3V

VOUT ≤ 0.6V

100

10.10.01

RMS OUTPUT NOISE (µV

RMS

)

3042 G47

SET PIN CAPACITANCE (µF)

VIN = 5V

RSET = 33.2kΩ

COUT = 4.7µF

IL = 200mA

OUTPUT NOISE (nV/√Hz)

100

0.1

3042 G51

FREQUENCY (Hz)

10 100 1k 1M

10M

100k10k

VIN = 5V

RSET = 33.2kΩ

CSET = 4.7µF

COUT = 4.7µF

IL = 200mA

IL = 100mA

IL = 50mA

IL = 1mA

INPUT-TO-OUTPUT DIFFERENTIAL (V)

PSRR (dB)

100

3042 G45

012

IL = 200mA

RSET = 33.2kΩ

COUT = 4.7µF

CSET = 0.47µF

100kHz

500kHz

1MHz

2MHz

RMS OUTPUT NOISE (µV

RMS)

2.0

0.2

1.8

1.4

1.0

0.6

1.6

1.2

0.8

0.4

OUTPUT VOLTAGE (V)

0 7.5 13.54.5 10.5

3042 G48

156 123 91.5

VIN = VOUT + 2V

CSET = 4.7µF

COUT = 4.7µF

ILOAD = 200mA

OUTPUT NOISE (nV/√Hz)

1000

100

0.1

3042 G49

FREQUENCY (Hz)

10 100 1k 1M

10M

100k10k

VIN = 5V

RSET = 33.2kΩ

COUT = 4.7µF

IL = 200mA

CSET = 0.047µF

CSET = 0.47µF

CSET = 1µF

CSET = 4.7µF

CSET = 22µF

OUTPUT NOISE (NJ/mi) LT3042 I000 y__ W ‘ [F— \ ,/7V\/, sunmwulv ﬂ \ \ /\ ‘I‘I

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Noise Spectral Density as

a Function of Error Amplifier

Input Pair

OUTPUT NOISE (nV/√Hz)

1000

100

0.1

3042 G52

FREQUENCY (Hz)

10 100 1k 1M

10M

100k10k

VIN = VOUT + 2V

IL = 200mA

COUT = 4.7µF

CSET = 4.7µF

VOUT ≥ 1.3V

0.6V < VOUT < 1.3V

VOUT ≤ 0.6V

TYPICAL PERFORMANCE CHARACTERISTICS

Start-Up Time with and

without Fast Start-Up Circuitry for

Large CSET

Input Supply Ramp-Up and

Ramp-Down

Output Noise: 10Hz to 100kHz Load Transient Response

Line Transient Response

TJ = 25°C, unless otherwise noted.

5µV/DIV

1ms/DIV

3042 G53

VIN = 5V

RSET = 33.2kΩ

COUT = 4.7µF

CSET = 4.7µF

= 200mA

200mA/DIV

10mV/DIV

20µs/DIV

3042 G54

VIN = 5V

RSET = 33.2kΩ

COUT = 4.7µF

CSET = 0.47µF

LOAD STEP = 10mA TO 200mA

LOAD STEP

OUTPUT VOLTAGE

500mV/DIV

1mV/DIV

5µs/DIV

3042 G55

VIN = 4V TO 4.5V

RSET = 33.2kΩ

COUT = 4.7µF

CSET = 0.47µF

IL = 200mA

OUTPUT VOLTAGE

INPUT VOLTAGE

500mV/DIV

2V/DIV

100ms/DIV 3042 G56

IN = 5V

SET = 33.2kΩ

OUT = 4.7µF

SET = 4.7µF

L = 16.5Ω

PULSE EN/UV

OUTPUT WITH

FAST START-UP

(SET AT 95%)

OUTPUT WITHOUT

FAST START-UP

2V/DIV

50ms/DIV

3042 G57

VIN = 0V TO 5V

RSET = 33.2kΩ

COUT = 4.7µF

CSET = 0.47µF

= 16.5Ω

OUTPUT VOLTAGE

INPUT VOLTAGE

LT3042 12

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PIN FUNCTIONS

IN (Pins 1, 2): Input. These pins supply power to the

regulator. The LT3042 requires a bypass capacitor at the

IN pin. In general, a battery’s output impedance rises with

frequency, so include a bypass capacitor in battery-powered

applications. While a 4.7µF input bypass capacitor gener-

ally suffices, applications with large load transients may

require higher input capacitance to prevent input supply

droop. Consult the Applications Information section on the

proper use of an input capacitor and its effect on circuit

performance, in particular PSRR. The LT3042 withstands

reverse voltages on IN with respect to GND, OUTS and OUT.

In the case of a reversed input, which occurs if a battery

is plugged-in backwards, the LT3042 acts as if a diode is

in series with its input. Hence, no reverse current flows

into the LT3042 and no negative voltage appears at the

load. The device protects itself and the load.

EN/UV (Pin 3): Enable/UVLO. Pulling the LT3042’s EN/UV

pin low places the part in shutdown. Quiescent current in

shutdown drops to less than 1µA and the output voltage

turns off. Alternatively, the EN/UV pin can set an input

supply undervoltage lockout (UVLO) threshold using a

resistor divider between IN, EN/UV and GND. The LT3042

typically turns on when the EN/UV voltage exceeds 1.24V

on its rising edge, with a 170mV hysteresis on its falling

edge. The EN/UV pin can be driven above the input voltage

and maintain proper functionality. If unused, tie EN/UV to

IN. Do not float the EN/UV pin.

PG (Pin 4): Power Good. PG is an open-collector flag that

indicates output voltage regulation. PG pulls low if PGFB

is below 300mV. If the power good functionality is not

needed, float the PG pin. A parasitic substrate diode exists

between PG and GND pins of the LT3042; do not drive

PG more than 0.3V below GND during normal operation

or during a fault condition.

ILIM (Pin 5): Current Limit Programming Pin. Connecting

a resistor between ILIM and GND programs the current

limit. For best accuracy, Kelvin connect this resistor directly

to the LT3042’s GND pin. The programming scale factor

is nominally 125mA•kΩ. The ILIM pin sources current

proportional (1:400) to output current; therefore, it also

serves as a current monitoring pin with a 0V to 300mV

range. If the programmable current limit functionality is

not needed, tie ILIM to GND. A parasitic substrate diode

exists between ILIM and GND pins of the LT3042; do not

drive ILIM more than 0.3V below GND during normal

operation or during a fault condition.

PGFB (Pin 6): Power Good Feedback. The PG pin pulls

high if PGFB increases beyond 300mV on its rising edge,

with 7mV hysteresis on its falling edge. Connecting an

external resistor divider between OUT, PGFB and GND

sets the programmable power good threshold with the

following transfer function: 0.3V • (1 + RPG2/RPG1). As

discussed in the Applications Information section, PGFB

also activates the fast start-up circuitry. Tie PGFB to IN

if power good and fast start-up functionalities are not

needed, and if reverse input protection is additionally

required, tie the anode of a 1N4148 diode to IN and its

cathode to PGFB. See the Typical Applications section for

details. A parasitic substrate diode exists between PGFB

and GND pins of the LT3042; do not drive PGFB more

than 0.3V below GND during normal operation or during

a fault condition.

SET (Pin 7): SET. This pin is the inverting input of the error

amplifier and the regulation set-point for the LT3042. SET

sources a precision 100µA current that flows through an

external resistor connected between SET and GND. The

LT3042’s output voltage is determined by VSET = ISET •RSET.

Output voltage range is from zero to 15V. Adding a capaci-

tor from SET to GND improves noise, PSRR and transient

response at the expense of increased start-up time. For

optimum load regulation, Kelvin connect the ground side

of the SET pin resistor directly to the load. A parasitic

substrate diode exists between SET and GND pins of the

LT3042; do not drive SET more than 0.3V below GND

during normal operation or during a fault condition.

GND (Pin 8, Exposed Pad Pin 11): Ground. The exposed

backside is an electrical connection to GND. To ensure

proper electrical and thermal performance, solder the

exposed backside to the PCB ground and tie it directly to

the GND pin.

LT3042 13

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For more information www.linear.com/LT3042

PIN FUNCTIONS

BLOCK DIAGRAM

–

OUTPUT OVERSHOOT

RECOVERY

ERROR

AMPLIFIER

INTERNAL CURRENT

LIMIT

PROGRAMMABLE

CURRENT LIMIT

QC QP

OUT

1.5V

100µA

2mA

–

300mV

270Ω

QPWR

–

DRIVER

–

300mV

ILIM

–

1, 2

THERMAL

SHDN

CURRENT

REFERENCE

FAST START-UP

INPUT

UVLO

SET-TO-OUTS

PROTECTION

CLAMP

INPUT UVLO

CURRENT LIMIT

THERMAL SHDN

DROPOUT

SET

PG2

PG1

SET

–

FAST START-UP

DISABLE LOGIC

OUTS

3042 BD

SET

PGFB

EN/UV

GND

–

300mV

–

1.24V

PROGRAMMABLE

POWER GOOD

–

ENABLE

COMPARATOR

BIAS

OUTS (Pin 9): Output Sense. This pin is the noninvert-

ing input to the error amplifier. For optimal transient

performance and load regulation, Kelvin connect OUTS

directly to the output capacitor and the load. Also, tie the

GND connections of the output capacitor and the SET

pin capacitor directly together

. Moreover, place the input

and output capacitors (and their GND connections) very

close together. A parasitic substrate diode exists between

OUTS and GND pins of the LT3042; do not drive OUTS

more than 0.3V below GND during normal operation or

during a fault condition.

OUT (Pin 10): Output. This pin supplies power to the load.

For stability, use a minimum 4.7µF output capacitor with

an ESR below 50mΩ and an ESL below 2nH. Large load

transients require larger output capacitance to limit peak

voltage transients. Refer to the Applications Information

section for more information on output capacitance. A

parasitic substrate diode exists between OUT and GND pins

of the LT3042; do not drive OUT more than 0.3V below

GND during normal operation or during a fault condition.

LT3042 14

LT3042

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For more information www.linear.com/LT3042

APPLICATIONS INFORMATION

The LT3042 is a high performance low dropout linear

regulator featuring LTC’s ultralow noise (2nV/√Hz at

10kHz) and ultrahigh PSRR (79dB at 1MHz) architecture

for powering noise sensitive applications. Designed as a

precision current source followed by a high performance

rail-to-rail voltage buffer, the LT3042 can be easily paral-

leled to further reduce noise, increase output current and

spread heat on the PCB. The device additionally features

programmable current limit, fast start-up capability and

programmable power good.

The LT3042 is easy to use and incorporates all of the

protection features expected in high performance regula-

tors. Included are short-circuit protection, safe operating

area protection, reverse battery protection, reverse current

protection, and thermal shutdown with hysteresis.

Output Voltage

The LT3042 incorporates a precision 100µA current source

flowing out of the SET pin, which also ties to the error

amplifier’s inverting input. Figure1 illustrates that connect-

ing a resistor from SET to ground generates a reference

voltage for the error amplifier. This reference voltage is

simply the product of the SET pin current and the SET

pin resistor. The error amplifier’s unity-gain configuration

produces a low impedance version of this voltage on its

noninverting input, i.e. the OUTS pin, which is externally

tied to the OUT pin.

The LT3042’s rail-to-rail error amplifier and current refer-

ence allows for a wide output voltage range from 0V (us-

ing a 0Ω resistor) to VIN minus dropout — up to 15V. A

PNP-based input pair is active for 0V to 0.6V output and an

NPN-based input pair is active for output voltages greater

than 1.3V, with a smooth transition between the two input

pairs from 0.6V to 1.3V output. While the NPN-based input

pair is designed to offer the best overall performance, refer

to the Electrical Characteristics Table for details on offset

voltage, SET pin current, output noise and PSRR variation

with the error amp input pair. Table 1 lists many common

output voltages and their corresponding 1% RSET resistors.

Table 1. 1% Resistor for Common Output Voltages

VOUT (V) RSET (kΩ)

2.5 24.9

3.3 33.2

5 49.9

12 121

15 150

The benefit of using a current reference compared with

a voltage reference as used in conventional regulators is

that the regulator always operates in unity gain configura-

tion, independent of the programmed output voltage. This

allows the LT3042 to have loop gain, frequency response

and bandwidth independent of the output voltage. As a

result, noise, PSRR and transient performance do not

change with output voltage. Moreover, since none of the

error amp gain is needed to amplify the SET pin voltage

to a higher output voltage, output load regulation is more

tightly specified in the hundreds of microvolts range and

not as a fixed percentage of the output voltage.

Since the zero TC current source is highly accurate, the

SET pin resistor can become the limiting factor in achiev-

ing high accuracy. Hence, it should be a precision resistor.

Additionally, any leakage paths to or from the SET pin

create errors in the output voltage. If necessary, use high

quality insulation (e.g., Teflon, Kel-F); moreover, clean-

ing of all insulating surfaces to remove fluxes and other

residues may be required. High humidity environments

may require a surface coating at the SET pin to provide

a moisture barrier

Minimize board leakage by encircling the SET pin with a

guard ring operated at a potential close to itself — ideally

tied to the OUT pin. Guarding both sides of the circuit

board is recommended. Bulk leakage reduction depends

on the guard ring width. Leakages of 100nA into or out of

–

100µA

EN/UV

PGFB

GND

OUT

LT3042

ILIM PG

4.7µF

5V ±5%

0.47µF

OUT,

3.3V

OUT(MAX)

, 200mA

3042 F01

33.2k

SET

OUTS

Figure1. Basic Adjustable Regulator

LTamz IPG LT3042 DEMO BOARD Vow launmxl mm" 15

LT3042

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APPLICATIONS INFORMATION

the SET pin creates a 0.1% error in the reference voltage.

Leakages of this magnitude, coupled with other sources

of leakage, can cause significant errors in the output volt-

age, especially over wide operating temperature range.

Figure2illustrates a typical guard ring layout technique.

requirements. While the LT3042 is robust enough not

to oscillate if the recommended layout is not followed,

depending on the actual layout, phase/gain margin, noise

and PSRR performance may degrade.

Stability and Output Capacitance

The LT3042 requires an output capacitor for stability.

Given its high bandwidth, LTC recommends low ESR and

ESL ceramic capacitors. A minimum 4.7µF output capaci-

tor with an ESR below 50mΩ and an ESL below 2nH is

required for stability.

Given the high PSRR and low noise performance attained

using a single 4.7µF ceramic output capacitor, larger values

of output capacitor only marginally improves the perfor-

mance because the regulator bandwidth decreases with

increasing output capacitance — hence, there is little to

be gained by using larger than the minimum 4.7µF output

capacitor. Nonetheless, larger values of output capacitance

do decrease peak output deviations during a load transient.

Note that bypass capacitors used to decouple individual

components powered by the LT3042 increase the effective

output capacitance.

Give extra consideration to the type of ceramic capacitors

used. They are manufactured with a variety of dielectrics,

each with different behavior across temperature and applied

voltage. The most common dielectrics used are specified

with EIA temperature characteristic codes of Z5U, Y5V,

3042 F02

OUT

SET

Figure2. Guard Ring Layout

Figure3. COUT and CSET Connections for Stability

Since the SET pin is a high impedance node, unwanted

signals may couple into the SET pin and cause erratic

behavior. This is most noticeable when operating with a

minimum output capacitor at heavy load currents. By-

passing the SET pin with a small capacitance to ground

resolves this issue — 10nF is sufficient.

For applications requiring higher accuracy or an adjust-

able output voltage, the SET pin may be actively driven

by an external voltage source capable of sinking 100µA.

Connecting a precision voltage reference to the SET pin

eliminates any errors present in the output voltage due

to the reference current and SET pin resistor tolerances.

Output Sensing and Stability

The LT3042’s OUTS pin provides a Kelvin sense connection

to the output. The SET pin resistor’s GND side provides a

Kelvin sense connection to the load’s GND side.

Additionally, for ultrahigh PSRR, the LT3042 bandwidth

is made quite high (~1MHz), making it close to a typical

4.7µF (1206 case size) ceramic output capacitor’s self-

resonance frequency (~2.3MHz). Therefore, it is very

important to avoid adding extra impedance (ESR and

ESL) outside the feedback loop. To that end, as shown

in Figure3, minimize the effects of PCB trace and solder

inductance by tying the OUTS pin directly to COUT and the

GND side of CSET directly to the GND side of COUT, as

well as keep the GND sides of CIN and COUT reasonably

close. Refer to the LT3042 demo board manual for more

information on the recommended layout that meets these

OUT

SET

OUT

SET

LT3042

DEMO BOARD

PCB LAYOUT

ILLUSTRATES

4-TERMINAL

CONNECTION

TO COUT

100µA

OUTS

ILIM

3042 F03

GND

PGFB

EN/UV

OUT

OUT(MAX)

: 200mA

LT3042 16 3 < x5r="" viv="">

LT3042

3042fb

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APPLICATIONS INFORMATION

X5R and X7R. The Z5U and Y5V dielectrics are good for

providing high capacitance in the small packages, but they

tend to have stronger voltage and temperature coefficients

as shown in Figure4 and Figure5. When used with a 5V

regulator, a 16V 10µF Y5V capacitor can exhibit an effective

value as low as 1µF to 2µF for the DC bias voltage applied

over the operating temperature range.

X5R and X7R dielectrics result in more stable character-

istics and are thus more suitable for LT3042. The X7R

dielectric has better stability across temperature, while

the X5R is less expensive and is available in higher values.

Nonetheless, care must still be exercised when using

X5R and X7R capacitors. The X5R and X7R codes only

specify operating temperature range and the maximum

capacitance change over temperature. While capacitance

change due to DC bias for X5R and X7R is better than

Y5V and Z5U dielectrics, it can still be significant enough

to drop capacitance below sufficient levels. As shown in

Figure6, capacitor DC bias characteristics tend to improve

as component case size increases, but verification of

expected capacitance at the operating voltage is highly

recommended.

High Vibration Environments

Voltage and temperature coefficients are not the only

sources of problems. Some ceramic capacitors have a

piezoelectric response. A piezoelectric device generates

voltage across its terminals due to mechanical stress upon

it, similar to how a piezoelectric microphone works. For a

ceramic capacitor, this stress can be induced by mechanical

vibrations within the system or due to thermal transients.

LT3042 applications in high vibration environments have

three distinct piezoelectric noise generators: ceramic

output, input, and SET pin capacitors. However, due to

LT3042’s very low output impedance over a wide fre-

quency range, negligible output noise is generated using

a ceramic output capacitor

. Similarly, due to LT3042’s

ultrahigh PSRR, negligible output noise is generated

using a ceramic input capacitor. Nonetheless, given the

high SET pin impedance, any piezoelectric response

from a ceramic SET pin capacitor generates significant

output noise – peak-to-peak excursions of hundreds of

µVs. However, due to the SET pin capacitor’s high ESR

Figure4. Ceramic Capacitor DC Bias Characteristics

Figure5. Ceramic Capacitor Temperature Characteristics

Figure6. Capacitor Voltage Coefficient for Different Case Sizes

DC BIAS VOLTAGE (V)

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

–100

CHANGE IN VALUE (%)

–80

642 810 12

3042 F04

–60

–40

X5R

Y5V

–20

TEMPERATURE (°C)

–50

–100

CHANGE IN VALUE (%)

–80

250–25 50 75 100

3042 F05

–60

–40 Y5V

–20

125

BOTH CAPACITORS ARE 16V,

1210 CASE SIZE, 10µF

X5R

DC BIAS (V)

–100

CHANGE IN VALUE (%)

–80

–60

–40

–20

5 10 15 20

3042 F06

1210, 2.2mm THICK

1206, 1.8mm THICK

0805, 1.4mm THICK

MURATA: X7R, 25V,4.7µF CERAMIC

LT3042 17

LT3042

3042fb

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APPLICATIONS INFORMATION

and ESL tolerance, any non-piezoelectrically responsive

(tantalum, electrolytic, or film) capacitor can be used at

the SET pin – although electrolytic capacitors tend to have

high 1/f noise. In any case, use of surface mount capacitor

is highly recommended.

Stability and Input Capacitance

The LT3042 is stable with a minimum 4.7µF IN pin capacitor.

LTC recommends using low ESR ceramic capacitors. In

cases where long wires connect the power supply to the

LT3042’s input and ground terminals, the use of low value

input capacitors combined with a large load current can

result in instability. The resonant LC tank circuit formed by

the wire inductance and the input capacitor is the cause

and not because of LT3042’s instability.

The self-inductance, or isolated inductance, of a wire

is directly proportional to its length. The wire diameter,

however, has less influence on its self-inductance. For

example, the self-inductance of a 2-AWG isolated wire

with a diameter of 0.26" is about half the inductance of a

30-AWG wire with a diameter of 0.01". One foot of 30-AWG

wire has 465nH of self-inductance.

Several methods exist to reduce a wire’s self-inductance.

One method divides the current flowing towards the LT3042

between two parallel conductors. In this case, placing the

wires further apart reduces the inductance; up to a 50%

reduction when placed only a few inches apart. Splitting

the wires connect two equal inductors in parallel. However,

when placed in close proximity to each other, their mu-

tual inductance adds to the overall self inductance of the

wires — therefore a 50% reduction is not possible in such

cases. The second and more effective technique to reduce

the overall inductance is to place the forward and return

current conductors (the input and ground wires) in close

proximity. Two 30-AWG wires separated by 0.02" reduce

the overall inductance to about one-fifth of a single wire.

If a battery mounted in close proximity powers the LT3042,

a 4.7µF input capacitor suffices for stability. However, if a

distantly located supply powers the LT3042, use a larger

value input capacitor. Use a rough guideline of 1µF (in

addition to the 4.7µF minimum) per 8" of wire length.

The minimum input capacitance needed to stabilize the

application also varies with the output capacitance as well

as the load current. Placing additional capacitance on the

LT3042’s output helps. However, this requires significantly

more capacitance compared to additional input bypassing.

Series resistance between the supply and the LT3042 input

also helps stabilize the application; as little as 0.1Ω to 0.5Ω

suffices. This impedance dampens the LC tank circuit at

the expense of dropout voltage. A better alternative is to

use a higher ESR tantalum or electrolytic capacitor at the

LT3042 input in parallel with a 4.7µF ceramic capacitor.

PSRR and Input Capacitance

For applications utilizing the LT3042 for post-regulating

switching converters, placing a capacitor directly at

the LT3042 input results in ac current (at the switching

frequency) to flow near the LT3042. This relatively high

frequency switching current generates a magnetic field

that couples to the LT3042 output, thereby degrading its

effective PSRR. While highly dependent on the PCB, the

switching pre-regulator, the input capacitance, amongst

other factors, the PSRR degradation can be easily over

30dB at 1MHz. This degradation is present even if the

LT3042 is de-soldered from the board, because it ef-

fectively degrades the PSRR of the PC board itself. While

negligible for conventional low PSRR LDOs, LT3042’s

ultrahigh PSRR requires careful attention to higher order

parasitics in order to extract the full performance offered

by the regulator.

To mitigate the flow of high-frequency switching current

near the LT3042, the LT3042 input capacitor can be entirely

removed—as long as the switching converter’s output

capacitor is located more than an inch away from the

LT3042. Magnetic coupling rapidly decreases with increas-

ing distance. Nonetheless, if the switching pre-regulator

is placed too far away (conservatively more than a couple

inches) from the LT3042, with no input capacitor present,

as with any regulator, the LT3042 input will oscillate at the

parasitic LC resonance frequency. Besides, it is generally a

very common (and a preferred) practice to bypass regula-

tor input with some capacitance. So this option is fairly

limited in its scope and not the most palatable solution.

LT3042 18

LT3042

3042fb

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APPLICATIONS INFORMATION

To that end, LTC recommends using the LT3042 demo

board (DC2246B) layout for achieving the best possible

PSRR performance. The LT3042 demo board layout

utilizes magnetic field cancellation techniques to prevent

PSRR degradation caused by this high-frequency current

flow—while utilizing the input capacitor.

Filtering High Frequency Spikes

For applications where the LT3042 is used to post-regulate

a switching converter, its high PSRR effectively sup-

presses any “noise” present at the switcher’s switching

frequency — typically 100kHz to 4MHz. However, the very

high frequency (100s of MHz) “spikes” — beyond the

LT3042’s bandwidth — associated with the switcher’s

power switch transition times will almost directly pass

through the LT3042. While the output capacitor is partly

intended to absorb these spikes, its ESL will limit its ability

at these frequencies. A ferrite bead or even the inductance

associated with a short (e.g. 0.5”) PCB trace between the

switcher’s output and the LT3042’s input can serve as an

LC-filter to suppress these very high frequency spikes.

Output Noise

The LT3042 offers many advantages with respect to noise

performance. Traditional linear regulators have several

sources of noise. The most critical noise sources for a

traditional regulator are its voltage reference, error amplifier,

noise from the resistor divider network used for setting

output voltage and the noise gain created by this resistor

divider. Many low noise regulators pin out their voltage

reference to allow for noise reduction by bypassing the

reference voltage.

Unlike most linear regulators, the LT3042 does not use a

voltage reference; instead, it uses a 100µA current refer-

ence. The current reference operates with typical noise

current level of 20pA/√Hz (6nARMS over a 10Hz to 100kHz

bandwidth). The resultant voltage noise equals the current

noise multiplied by the resistor value, which in turn is RMS

summed with the error amplifier’s noise and the resistor’s

own noise of √4kTR — whereby k = Boltzmann’s constant

1.38 • 10–23J/K and T is the absolute temperature.

One problem that conventional linear regulators face is

that the resistor divider setting the output voltage gains up

the reference noise. In contrast, the LT3042’s unity-gain

follower architecture presents no gain from the SET pin

to the output. Therefore, if a capacitor bypasses the SET

pin resistor, then the output noise is independent of the

programmed output voltage. The resultant output noise

is then set just by the error amplifier’s noise — typically

2nV/√Hz from 10kHz to 1MHz and 0.8µVRMS in a 10Hz to

100kHz bandwidth using a 4.7µF SET pin capacitor. Paral-

leling multiple LT3042s further reduces noise by √N, for

N parallel regulators.

Refer to the Typical Performance Characteristics section

for noise spectral density and RMS integrated noise over

various load currents and SET pin capacitances.

Set Pin (Bypass) Capacitance: Noise, PSRR, Transient

Response and Soft-Start

In addition to reducing output noise, using a SET pin bypass

capacitor also improves PSRR and transient performance.

Note that any bypass capacitor leakage deteriorates the

LT3042’s DC regulation. Capacitor leakage of even 100nA

is a 0.1% DC error. Therefore, LTC recommends the use

of a good quality low leakage ceramic capacitor.

Using a SET pin bypass capacitor also soft-starts the output

and limits inrush current. The RC time constant, formed

by the SET pin resistor and capacitor, controls soft-start

time. Ramp-up rate from 0 to 90% of nominal VOUT is:

tSS ≈ 2.3 • RSET • CSET (fast start-up disabled)

Fast Start-Up

For ultralow noise applications that require low 1/f noise

(i.e. at frequencies below 100Hz), a larger value SET pin

capacitor is required, up to 22µF. While normally this would

significantly increase the regulator’s start-up time, the

LT3042 incorporates fast start-up circuitry that increases

the SET pin current to about 2mA during start-up.

As shown in the Block Diagram, the 2mA current source

remains engaged while PGFB is below 300mV, unless the

regulator is in current limit, dropout, thermal shutdown

or input voltage is below minimum VIN.

If fast start-up capability is not used, tie PGFB to IN or to

OUT for output voltages above 300mV. Note that doing

so also disables power good functionality.

LT3042 ENZ \ EM} P62 19

LT3042

3042fb

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APPLICATIONS INFORMATION

ENABLE/UVLO

The EN/UV pin is used to put the regulator into a mi-

cropower shutdown state. The LT3042 has an accurate

1.24V turn-on threshold on the EN/UV pin with 170mV

of hysteresis. This threshold can be used in conjunction

with a resistor divider from the input supply to define an

accurate undervoltage lockout (UVLO) threshold for the

regulator. The EN/UV pin current (IEN) at the threshold from

the Electrical Characteristics table needs to be considered

when calculating the resistor divider network:

VIN(UVLO) =1.24V • 1+REN2

EN1

⎛

⎝

⎜

⎞

⎠

⎟+IEN •REN2

The EN/UV pin current (IEN) can be ignored if REN1 is less

than 100k. If unused, tie EN/UV pin to IN.

Programmable Power Good

As illustrated in the Block Diagram, power good thresh-

old is user programmable using the ratio of two external

resistors, RPG2 and RPG1:

VOUT(PG_ THRESHOLD) =0.3V • 1+RPG2

PG1

⎛

⎝

⎜

⎞

⎠

⎟+IPGFB •RPG2

If the PGFB pin increases above 300mV, the open-collector

PG pin de-asserts and becomes high impedance. The

power good comparator has 7mV hysteresis and 5µs of

deglitching. The PGFB pin current (IPGFB) from the Electrical

Characteristics table must be considered when determining

the resistor divider network. The PGFB pin current (IPGFB)

can be ignored if RPG1 is less than 30k. If power good

functionality is not used, float the PG pin. Please note that

programmable power good and fast start-up capabilities

are disabled for output voltages below 300mV or when

the device is in shutdown.

Externally Programmable Current Limit

The ILIM pin’s current limit threshold is 300mV. Connecting

a resistor from ILIM to GND sets the maximum current

flowing out of the ILIM pin, which in turn programs the

LT3042’s current limit. With a 125mA • kΩ programming

scale factor, the current limit can be calculated as follows:

Current Limit = 125mA • kΩ/R

ILIM

For example, a 1kΩ resistor programs the current limit to

125mA and a 2kΩ resistor programs the current limit to

62.5mA. For good accuracy, Kelvin connect this resistor

to the LT3042’s GND pin.

In cases where IN-to-OUT differential is greater than 12V,

the LT3042’s foldback circuitry decreases the internal

current limit. As a result, internal current limit may over-

ride the externally programmed current limit level to keep

the LT3042 within its safe-operating-area (SOA). See the

Internal Current Limit vs Input-to-Output Differential graph

in the Typical Performance Characteristics section.

As shown in the Block Diagram, the ILIM pin sources current

proportional (1:400) to output current; therefore, it also

serves as a current monitoring pin with a 0V to 300mV

range. If external current limit or current monitoring is

not used, tie ILIM to GND.

Output Overshoot Recovery

During a load step from full load to no load (or light

load), the output voltage overshoots before the regulator

responds to turn the power transistor OFF. Given that there

is no load (or very light load) present at the output, it takes

a long time to discharge the output capacitor.

As illustrated in the Block Diagram, the LT3042 incorporates

an overshoot recovery circuitry that turns on a current

sink to discharge the output capacitor in the event OUTS

is higher than SET. This current is typically about 4mA.

No load recovery is disabled for input voltages less than

2.5V or output voltages less than 1.5V.

If OUTS is externally held above SET, the current sink

turns ON in an attempt to restore OUTS to its programmed

voltage. The current sink remains ON until the external

circuitry releases OUTS.

Direct Paralleling for Higher Current

Higher output current is obtained by paralleling multiple

LT3042s. Tie all SET pins together and all IN pins together.

Connect the OUT pins together using small pieces of PCB

trace (used as a ballast resistor) to equalize currents in

the LT3042s. PCB trace resistance in milliohms/inch is

shown in Table 2.

LT3042 2O

LT3042

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APPLICATIONS INFORMATION

PCB Layout Considerations

Given the LT3042’s high bandwidth and ultrahigh PSRR,

careful PCB layout must be employed to achieve full

device performance. Figure8 shows an example layout

that delivers full performance of the regulator. Refer to the

LT3042’s DC2246B demo board manual for further details.

Figure8. Example DFN Layout

Table 2. PC Board Trace Resistance

WEIGHT (oz) 10mil WIDTH 20mil WIDTH

1 54.3 27.1

2 27.1 13.6

Trace resistance is measured in mΩ/in.

The small worst-case offset of 2mV for each paralleled

LT3042 minimizes the required ballast resistor value.

Figure7 illustrates that two LT3042s, each using a 50mΩ

PCB trace ballast resistor, provide better than 20% ac-

curate output current sharing at full load. The two 50mΩ

external resistors only add 10mV of output regulation drop

with a 400mA maximum current. With a 3.3V output, this

only adds 0.3% to the regulation accuracy. As has been

discussed previously, tie the OUTS pin directly to the

output capacitor.

More than two LT3042s can also be paralleled for even

higher output current and lower output noise. Paralleling

multiple LT3042s is also useful for distributing heat on the

PCB. For applications with high input-to-output voltage

differential, an input series resistor or resistor in parallel

with the LT3042 can also be used to spread heat.

–

100µA

EN/UV

PGFB

GND

OUT

LT3042

ILIM PG 4.7µF

50mΩ

VOUT

3.3V

OUT(MAX)

400mA

3042 F07

16.5k

SET

OUTS

–

100µA

EN/UV

PGFB

GND

OUT

LT3042

ILIM PG 4.7µF

50mΩ

10µF

VIN

5V ±5%

SET

OUTS

0.47µF

Figure7. Parallel Devices

3042 F08

LT3042 21

LT3042

3042fb

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Thermal Considerations

The LT3042 has internal power and thermal limiting circuits

that protect the device under overload conditions. The

thermal shutdown temperature is nominally 162°C with

about 8°C of hysteresis. For continuous normal load condi-

tions, do not exceed the maximum junction temperature,

(125°C for E-, I-grades and 150°C for H-, MP-grades). It

is important to consider all sources of thermal resistance

from junction to ambient. This includes junction-to-case,

case-to-heat sink interface, heat sink resistance or circuit

board-to-ambient as the application dictates. Additionally,

consider all heat sources in close proximity to the LT3042.

The undersides of the DFN and MSOP packages have

exposed metal from the lead frame to the die attachment.

Both packages allow heat to directly transfer from the die

junction to the PCB metal to limit maximum operating

junction temperature. The dual-in-line pin arrangement

allows metal to extend beyond the ends of the package

on the topside (component side) of the PCB.

For surface mount devices, heat sinking is accomplished

by using the heat spreading capabilities of the PCB and its

copper traces. Copper board stiffeners and plated through-

holes can also be used to spread the heat generated by

the regulator.

Tables 3 and 4 list thermal resistance as a function of copper

area on a fixed board size. All measurements were taken

in still air on a 4 layer FR-4 board with 1oz solid internal

planes and 2oz top/bottom planes with a total board thick-

ness of 1.6mm. The four layers were electrically isolated

with no thermal vias present. PCB layers, copper weight,

board layout and thermal vias affect the resultant thermal

resistance. For more information on thermal resistance

and high thermal conductivity test boards, refer to JEDEC

standard JESD51, notably JESD51-7 and JESD51-12.

Achieving low thermal resistance necessitates attention

to detail and careful PCB layout.

Table 3. Measured Thermal Resistance for DFN Package

COPPER AREA

BOARD AREA

THERMAL

RESISTANCETOP SIDE* BOTTOM SIDE

2500mm22500mm22500mm234°C/W

1000mm22500mm22500mm234°C/W

225mm22500mm22500mm235°C/W

100mm22500mm22500mm236°C/W

*Device is mounted on topside

Table 4. Measured Thermal Resistance for MSOP Package

COPPER AREA

BOARD AREA

THERMAL

RESISTANCETOP SIDE* BOTTOM SIDE

2500mm22500mm22500mm233°C/W

1000mm22500mm22500mm233°C/W

225mm22500mm22500mm234°C/W

100mm22500mm22500mm235°C/W

*Device is mounted on topside

Calculating Junction Temperature

Example: Given an output voltage of 2.5V and input voltage

of 5V ± 5%, output current range from 1mA to 200mA,

and a maximum ambient temperature of 85°C, what is the

maximum junction temperature?

The LT3042’s power dissipation is:

IOUT(MAX) • (VIN(MAX) – VOUT) + IGND • VIN(MAX)

where:

IOUT(MAX) = 200mA

VIN(MAX) = 5.25V

IGND (at IOUT = 200mA and VIN = 5.25V) = 7.2mA

thus:

PDISS = 0.2A • (5.25V – 2.5V) + 7.2mA • 5.25V = 0.59W

Using a DFN package, the thermal resistance is in the

range of 34°C/W to 36°C/W depending on the copper area.

Therefore, the junction temperature rise above ambient

approximately equals:

0.59W • 35°C/W = 20.7°C

APPLICATIONS INFORMATION

LT3042

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APPLICATIONS INFORMATION

The maximum junction temperature equals the maxi-

mum ambient temperature plus the maximum junction

temperature rise above ambient:

TJMAX = 85°C + 20.7°C = 105.7°C

Overload Recovery

Like many IC power regulators, the LT3042 incorporates

safe-operating-area (SOA) protection. The SOA protection

activates at input-to-output differential voltages greater

than 12V. The SOA protection decreases the current limit

as the input-to-output differential increases and keeps

the power transistor inside a safe operating region for

all values of input-to-output voltages up to the LT3042’s

absolute maximum ratings. The LT3042 provides some

level of output current for all values of input-to-output dif-

ferentials. Refer to the Current Limit curves in the Typical

Performance Characteristics section. When power is first

applied and input voltage rises, the output follows the input

and keeps the input-to-output differential low to allow the

regulator to supply large output current and start-up into

high current loads.

Due to current limit foldback, however, at high input volt-

ages a problem can occur if the output voltage is low and

the load current is high. Such situations occur after the

removal of a short-circuit or if the EN/UV pin is pulled high

after the input voltage has already turned ON. The load line

in such cases intersects the output current profile at two

points. The regulator now has two stable operating points.

With this double intersection, the input power supply may

need to be cycled down to zero and brought back up again

to make the output recover. Other linear regulators with

foldback current limit protection (such as the LT1965 and

LT1963A, etc.) also exhibit this phenomenon, so it is not

unique to the LT3042.

Protection Features

The LT3042 incorporates several protection features for

battery-powered applications. Precision current limit and

thermal overload protection protect the LT3042 against

overload and fault conditions at the device’s output. For

normal operation, do not allow the junction temperature

to exceed 125°C (E-, I-grade) or 150°C (H-, MP-grade).

To protect the LT3042’s low noise error amplifier, the SET-

to-OUTS protection clamp limits the maximum voltage

between SET and OUTS with a maximum DC current of

20mA through the clamp. So for applications where SET

is actively driven by a voltage source, the voltage source

must be current limited to 20mA or less. Moreover, to limit

the transient current flowing through these clamps during

a transient fault condition, limit the maximum value of the

SET pin capacitor (CSET) to 22µF.

The LT3042 also incorporates reverse input protection

whereby the IN pin withstands reverse voltages of up to

–20V without causing any input current flow and without

developing negative voltages at the OUT pin. The regulator

protects both itself and the load against batteries that are

plugged-in backwards.

In circuits where a backup battery is required, several

different input/output conditions can occur. The output

voltage may be held up while the input is either pulled to

GND, pulled to some intermediate voltage, or left open-

circuit. In all of these cases, the reverse current protection

circuitry prevents current flow from output to the input.

Nonetheless, due to the OUTS-to-SET clamp, unless the

SET pin is floating, current can flow to GND through the

SET pin resistor as well as up to 15mA to GND through

the output overshoot recovery circuitry. This current flow

through the output overshoot recovery circuitry can be

significantly reduced by placing a Schottky diode between

OUTS and SET pins, with its anode at the OUTS pin.

LT3042 100 A-R 23

LT3042

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TYPICAL APPLICATIONS

12VIN to 3.3VOUT with 0.8µVRMS Integrated Noise

100µA

EN/UV

GND

OUT

LT3042

ILIM PGFB

453k

4.7µF

VIN

12V ±5%

200k

4.7µF

VOUT

3.3V

OUT(MAX)

100mA

49.9k

3042 TA02

33.2k

SET

OUTS

–

Low Noise CC/CV Lab Power Supply

PGFB Disabled without Reverse Input Protection PGFB Disabled with Reverse Input Protection

RSET

4.7µF

0.47µF

4.7µF

OUT

SET

LT3042

OUT

100µA

OUTS

PGFB

ILIM

GND

EN/UV

–

3042 TA03

0.47µF

4.7µF

1N4148

4.7µF

RSET

OUT

SET

LT3042

OUT

100µA

OUTS

PGFB

ILIM

GND

EN/UV

3042 TA04

–

4.7µF

0.47µF

4.7µF

RSET

IOUT

OUT

SET

LT3042

OUT

100µA

OUTS

PGFB

ILIM

GND

EN/UV

3042 TA05

–

OUT(MAX) =

100

A•R

SET

IOUT(MAX) =125mA •kΩ

RIOUT

LT3042 Vw 4v 1mm 34v mmrorr VuuT 3 3V Mummy 200qu Vw 5 av 10 zuv A M f

LT3042

3042fb

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TYPICAL APPLICATIONS

Programming Undervoltage Lockout

4.7µF

33.2k

0.47µF

REN2

110k

REN1

49.9k

4.7µF

4V Turn-ON

3.4V Turn-OFF

OUT

SET

LT3042

OUT

3.3V

OUT(MAX)

200mA

100µA

OUTS

EN/UV

ILIM

GND

PGFB

3042 TA06

–

VIN(UVLO) =1.24V •1+110k

49.9k

⎛

⎝

⎜

⎞

⎠

⎟

Ratiometric Tracking

4.7µF

0.1µF

4.7µF

33.2k

4.7µF

0.1µF

16.9k

5.5V TO 20V

OUT

SET

LT3042

OUT

3.3V

MIN LOAD 200µA

100µA

OUTS

PGFB

ILIM

GND

EN/UV

OUT

SET

LT3042

OUT

100µA

OUTS

PGFB

ILIM

GND

EN/UV

3042 TA07

–

LT3042 Vum = 5v ‘uunMAx, V 2 6‘7 ZOOMA LTCGE5575 4 7% 31.5 J. N=NUMBER DFDEVLCESW PARALLEL R R M zlzsmA-m/LLLWR D-N R ABLE (BALLAST RESLST ) R URRENT LLMLT PROGR r R E z n pane/N away = BALLAST RESISTOR \LIM = OUTPUT CURRENT LLMLT 25

LT3042

3042fb

For more information www.linear.com/LT3042

TYPICAL APPLICATIONS

Paralleling Multiple Devices Using ILIM (Current Monitor) to Cancel Ballast Resistor Drop

Ultralow 1/f Noise Reference Buffer

4.7µF

OUT

SET

LT3042

OUT

= 5V

OUT(MAX)

200mA

100µA

OUTS

PGFB

ILIM

GND

EN/UV

LTC6655-5

3042 TA08

–

1,2

3,4,5

6,7

10µF

49.9k

VIN

6V ±5%

4.7µF

N = NUMBER OF DEVICES IN PARALLEL

RCDC = CABLE (BALLAST RESISTOR) DROP CANCELLATION RESISTOR

RILIM = CURRENT LIMIT PROGRAMMING RESISTOR

RBALLAST = BALLAST RESISTOR

ILIM = OUTPUT CURRENT LIMIT

4.7µF

50mΩ

1µF

22µF

OUT

SET

LT3042

100µA

OUTS

PGFB

ILIM

GND

EN/UV

PGFB

EN/UV

–

16.5k

RILIM

549Ω

RCDC

10Ω

RILIM = 125mA • kΩ/ILIM – RCDC • N

= 549Ω (FOR 200mA ILIM PER REGULATOR)

RCDC = RBALLAST • 400/N

= 10Ω

VOUT = 3.3V

IOUT(MAX) = 400mA

549Ω

50mΩ

–

3042 TA09

OUT

LT3042

OUTS

SET

ILIM

GND

VIN

5V ±5%

LT3042 DRUPDUT: saumv 3w 3 iv 5mm 5mm 4 NF 4 7w ? 4 NF 3 25k

LT3042

3042fb

For more information www.linear.com/LT3042

TYPICAL APPLICATIONS

Paralleling Multiple LT3042s for Higher Output Current

4.7µF

50mΩ

4.7µF

OUT

SET

LT3042

100µA

OUTS

PGFB

ILIM

GND

EN/UV

PGFB

EN/UV

–

8.25k

50mΩ

–

3042 TA10

OUT

LT3042

OUTS

SET

ILIM

GND

4.7µF

50mΩ

4.7µF

OUT

SET

LT3042

100µA

OUTS

PGFB

GND

EN/UV

PGFB

EN/UV

–

453k

200k

49.9k

VOUT = 3.3V

IOUT(MAX) = 800mA

DROPOUT = 350mV

50mΩ

–

OUT

PNP

LT3042

OUTS

SET

ILIM

GND

OUTPUT NOISE =

0.8µV

RMS

=0.4µVRMS

VIN

5V ±5%

LT3042 DASVHmG t5ak 43 9k Vum 3 3v ‘uunmxI ‘ 5A mur I 4 M DMVHW Vow — ‘auwm mm m 27

LT3042

3042fb

For more information www.linear.com/LT3042

Ultralow Noise Higher Current Regulator with External NPN

10µF

4.7µF

47µF

20k

10k

10µF

4.7µF

750Ω

D44VH10

249k

49.9k

OUT

SET

LT3042

OUT

OUT(MAX)

100µA

OUTS

ILIM

GND

EN/UV

3042 TA12

–

PGFB

VIN

5V ±5%

Ultralow Noise Higher Current Regulator with External PNP

10µF

4.7µF

47µF

33.2k

10Ω

0.2Ω

22µF

D45VH10G

750Ω

150k

49.9k

OUT

SET

LT3042

OUT

3.3V

OUT(MAX)

1.5A

100µA

OUTS

PGFB

ILIM

GND

EN/UV

3042 TA11

–

VIN

5.5V ±5%

TYPICAL APPLICATIONS

LT3042 mm NOISE 20w 51‘qu m mam) RESISTORE KRIDGE P3“ uaIsEATv NaIsEATv PERFECT Vw M WFW‘TE 5v me we was znnnv 3m! 4 m 5% zeua mounv 42.5w v0“ 33v AND WWW) 200qu

LT3042

3042fb

For more information www.linear.com/LT3042

TYPICAL APPLICATIONS

Low Noise Wheatstone Bridge Power Supply

4.7µF

33.2k

4.7µF

200k

453k

49.9k

3042 TA13

4.7µF

–

5V ±5%

OUT

SET

LT3042

OUT

: 3.3V AND I

OUT(MAX)

: 200mA

100µA

OUTS

PGFB

ILIM

GND

EN/UV

RESISTOR

TOLERANCE

BRIDGE PSRR

NOISE AT VBRIDGE

USING LT1763

40dB

26dB

8nVRMS

42.5nVRMS

PERFECT

MATCHING

INFINITE

–

NOISE AT VBRIDGE

USING LT3042

200nVRMS

1000nVRMS

–

LT1763 NOISE: 20µVRMS (10Hz TO 100kHz)

LT3042 NOISE: 0.8µVRMS (10Hz TO 100kHz)

VBRIDGE

–

‘ T i 1 UUW L, 747,, "L7, 7‘ w 1 , ‘0 1 mm M it i, 71 F 9‘ VDDDDDi‘f LT3042 29

LT3042

3042fb

For more information www.linear.com/LT3042

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LT3042#packaging for the most recent package drawings.

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).

CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE

TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.125

TYP

2.38 ±0.10

(2 SIDES)

106

PIN 1

TOP MARK

(SEE NOTE 6)

0.200 REF

0.00 – 0.05

(DD) DFN REV C 0310

0.25 ±0.05

2.38 ±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

1.65 ±0.05

(2 SIDES)2.15 ±0.05

0.50

BSC

0.70 ±0.05

3.55 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05

0.50 BSC

DD Package

10-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1699 Rev C)

PIN 1 NOTCH

R = 0.20 OR

0.35 × 45°

CHAMFER

LT3042 \ 881mm (074 : mm [I 8&9 :0 ‘27 [035: 005) THEMED: (2T > 7 was 10m 32m 345 (ms 0041 (‘25 ‘36) Wm»i “5‘7 + (man

LT3042

3042fb

For more information www.linear.com/LT3042

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/product/LT3042#packaging for the most recent package drawings.

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev I)

MSOP (MSE) 0213 REV I

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

0.18

(.007)

1.10

(.043)

MAX

0.17 –0.27

(.007 – .011)

TYP

0.86

(.034)

REF

0.50

(.0197)

BSC

1234 5

4.90 ±0.152

(.193 ±.006)

0.497 ±0.076

(.0196 ±.003)

REF

8910

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.254

(.010) 0° – 6° TYP

DETAIL “A”

GAUGE PLANE

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

1.68 ±0.102

(.066 ±.004)

1.88 ±0.102

(.074 ±.004)

0.50

(.0197)

BSC

0.305 ± 0.038

(.0120 ±.0015)

TYP

BOTTOM VIEW OF

EXPOSED PAD OPTION

1.68

(.066)

1.88

(.074)

0.1016 ±0.0508

(.004 ±.002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

MSE Package

10-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1664 Rev I)

LT3042 31

LT3042

3042fb

For more information www.linear.com/LT3042

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 6/15 Updated text in the second paragraph

Updated Line Reg ∆VOS, Change in VOS, Output Noise Spectral Density specs

Updated text to clarify fast start-up test condition

Updated text to clarify Notes 5, 6, and 7

Updated text to clarify Note 10

Updated Graph 10 and Graph 12

Updated conditions on Graph 18 and Graph 24

Updated conditions on Graph 28

Updated title of Graph 40

Updated Output Voltage section

Updated Fast Start-up section

Modified Direct Paralleling for Higher Current section

Updated Typical Application circuit TA02

Added Equation text to the Typical Application circuit TA03

Updated Typical Application circuit TA06 and TA13

Updated text in the Typical Application circuit TA14 and TA07

Updated text in the Typical Application circuit TA08

14, 15

B 11/17 Modified Typical Application schematic.

Removed Ripple Rejection minimum spec in the Electrical Characteristics table.

Modified Start-Up Time conditions in the Electrical Characteristics table.

Revised Graph 37.

Changed scale on Graph 55.

Revised PGFB pin description in the Pin Functions section.

Modified Figure 3, and ‘Output Sensing and Stability’ and ‘Stability and Output Capacitance’ sections.

Added High Vibration Environments section.

Added PSRR + Input Capacitance section.

Revised Externally Programmable Current Limit section.

Revised Figure 8.

Modified Protection Features section.

LT3042 32 SEGLé’ES

LT3042

3042fb

For more information www.linear.com/LT3042

 ANALOG DEVICES, INC. 2017

LT 1117 REV B • PRINTED IN USA

www.linear.com/LT3042

RELATED PARTS

TYPICAL APPLICATION

–

100µA

EN/UV

PGFB

GND

OUT

LT3042

ILIM PG 4.7µF

50mΩ

VOUT

3.3V

OUT(MAX)

400mA

3042 TA14

16.5k

SET

OUTS

–

100µA

EN/UV

PGFB

GND

OUT

LT3042

ILIM PG 4.7µF

50mΩ

10µF

VIN

5V ±5%

SET

OUTS

0.47µF

Parallel Devices

PART NUMBER DESCRIPTION COMMENTS

LT1761 100mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µVRMS, VIN = 1.8V to 20V

LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20μVRMS, VIN = 1.8V to 20V,

SO-8 Package

LT3050 100mA LDO with Diagnostics and Precision Current Limit 340mV Dropout Voltage, Low Noise: 30μVRMS, VIN = 1.8V to 45V,

3mm × 2mm DFN and MSOP Packages

LT3060 100mA Low Noise LDO with Soft-Start 300mV Dropout Voltage, Low Noise: 30μVRMS, VIN = 1.8V to 45V,

2mm × 2mm DFN and ThinSOT Packages

LT3080 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40μVRMS,

VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with

1-Resistor VOUT Set; Directly Parallelable (No Op Amp Required),

Stable with Ceramic Capacitors; TO-220, DD-Pak, SOT-223, MSOP

and 3mm × 3mm DFN-8 Packages; LT3080-1 Version Has Integrated

Internal Ballast Resistor

LT3082 200mA, Parallelable, Low Noise LDO Outputs May Be Paralleled for Higher Output Current or Heat Spreading,

Wide Input Voltage Range: 1.2V to 40V, Low Value Input/Output

Capacitors Required: 2.2µF, Single Resistor Sets Output Voltage,

8-Lead SOT-23, 3-Lead SOT-223 and 8-Lead 3mm × 3mm DFN

Packages

LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear

Regulator

275mV Dropout (2-Supply Operation), Low Noise: 40μVRMS, VIN: 1.2V

to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor

VOUT Set, Directly Parallelable (No Op Amp Required), Stable with

Ceramic Capacitors; MS8E and 2mm × 3mm DFN-6 Packages

Fiche technique pour LT3042 de Analog Devices Inc.

INFORMATIONS

AIDE

NOUS CONTACTER

NOUS SUIVRE