Full-Bridge DMOS PWM Motor Drivers
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
The A4952 and A4953 are designed to operate DC motors. The
output drivers are all low-RDS(on) , N-channel DMOS drivers
that feature internal synchronous rectification to reduce power
dissipation. The current in the output full bridge is regulated with
fixed off-time pulse width modulated (PWM) control circuitry.
The IN1 and IN2 inputs allow two-wire control for the bridge.
Protection circuitry includes internal thermal shutdown, and pro-
tection against shorted loads, or against output shorts to ground
or supply. Undervoltage lockout prevents damage by keeping the
outputs off until the driver has enough voltage to operate nor-
Low Power Standby mode is activated when both input (INx)
pins are low for longer than 1 ms. Low Power Standby mode
disables most of the internal circuitry, including the charge pump
and the regulator. When the A4952/A4953 is coming out of
standby mode, the charge pump should be allowed to reach its
regulated voltage (a maximum delay of 30 µs) before any PWM
commands are issued to the device.
Internal PWM Current Control
Initially, a diagonal pair of source and sink FET outputs are
enabled and current flows through the motor winding and the
optional external current sense resistor, RS
. When the voltage
across RS equals the comparator trip value, then the current sense
comparator resets the PWM latch. The latch then turns off the
sink and source FETs (Mixed Decay mode).
The maximum value of current limiting is set by the selection of
RSx and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
ITripMAX (A), which is set by:
where VREF is the input voltage on the VREF pin (V) and RS is
In the A4952, a current monitor will protect the IC from damage
due to output shorts. The internal Overcurrent Protection (OCP)
has the following features:
• Fault Output (FLTn pin). If a short is detected, the open drain
FLTn output signal goes low.
• Retry Input (RTRY pin). Sets the action taken by the IC to re-
spond to an OCP fault. If the RTRY pin is tied to GND, then the
outputs will be turned-on again after a 2-ms timeout, to check
if a fault condition remains. If the RTRY pin is left open, then
the fault will be latched, and the IC will disable the outputs. The
fault latch can only be cleared by coming out of Low Power
Standby mode or by cycling the power to VBB.
Note: The A4953 overcurrent protection behaves in the same
manner but the fault is latched and can only be reset by putting
the device into standby mode or by cycling the power to VBB.
During OCP events, Absolute Maximum Ratings may be
exceeded for a short period of time before the device latches.
If the die temperature increases to approximately 160°C, the full
bridge outputs will be disabled until the internal temperature falls
below a hysteresis, TTSDhys , of 20°C. Internal UVLO is present
on VBB to prevent the output drivers from turning-on below the
The braking function is implemented by driving the device in
Slow Decay mode, which is done by applying a logic high to both
inputs, after a bridge-enable Chop command (see PWM Control
Truth Table). Because it is possible to drive current in both direc-
tions through the DMOS switches, this configuration effectively
shorts-out the motor-generated BEMF, as long as the Chop com-
mand is asserted. The maximum current can be approximated by
VBEMF / RL . Care should be taken to ensure that the maximum
ratings of the device are not exceeded in worse case braking situ-
ations: high speed and high-inertia loads.