The digital outputs of the LTM9001 have several selectable configurations for the parallel bus. The most significant one is the choice between differential LVDS or standard CMOS. With LVDS, you get lower EMI because of the lower signal swing on each line, yet improved noise margin because it is differential. Because the signals are not swinging from ground to the supply as in CMOS mode, there is less ground bounce and therefore less digital feedback that could affect the analog performance of the ADC. The drawbacks of LVDS are that twice as many traces are required on the board along with twice as many pins being required on the FPGA, it draws more supply current within the LTM9001, and it requires 100Ω parallel termination on each signal pair (although this is often integrated in the FPGA). Notice that the source termination is integrated in the digital output stage in either mode. In LVDS mode there is also a lower power option. The current is reduced in the driver stages which reduces the differential voltage created across the termination resistor. This lowers the overall power consumption at the expense of some of the noise margin. In CMOS mode, the LTM9001 can run at full rate on 16 data lines or demultiplex the data onto two 16-bit buses, lowering the bus speed. Another option for the CMOS mode is to lower the output supply voltage thereby reducing the voltage swing. This allows interfacing to 1.8V logic or future families that may be as low as 0.5V. The format of the data can also be selected as either offset binary or 2’s complement. The MODE selection also turns the clock duty cycle stabilizer on or off.