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TYPICAL APPLICATION
FEATURES DESCRIPTION
Wide Input Voltage Range
Boost/SEPIC/Inverting
Controller
2.5V to 36V Input, 12V Output SEPIC Converter
Excellent for Automotive 12V Post Regulator
APPLICATIONS
n Wide VIN Range: 1.6V to 42V
n Positive or Negative Output Voltage Programming
with a Single Feedback Pin
n PGOOD Output Voltage Status Report
n Accurate 50mV SENSE Threshold Voltage
n Programmable Soft-Start
n Programmable Operating Frequency (100kHz to 1MHz)
with One External Resistor
n Synchronizable to an External Clock
n Low Shutdown Current < 1µA
n INTVCC Regulator Supplied from VIN or DRIVE
n Programmable Input Undervoltage Lockout with
Hysteresis
n Datacom and Industrial Boost, SEPIC and Inverting
Converters
n Distributed Power Supplies
n Portable Electronic Equipment
n Automotive
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT and No RSENSE are trademarks of Linear Technology Corporation. All other trademarks
are the property of their respective owners. Protected by U.S. Patents including 7825665.
The LT
®
3759 is a wide input range, current mode, DC/DC
controller which is capable of regulating either positive or
negative output voltages from a single feedback pin. It can
be configured as a boost, SEPIC or inverting converter.
The LT3759 drives a low side external N-channel power
MOSFET. An internal LDO regulator draws power from
VIN or DRIVE to provide up to a 4.75V supply for the gate
driver. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages. The operating frequency of LT3759
can be set over a 100kHz to 1MHz range with an external
resistor, or can be synchronized to an external clock using
the SYNC pin.
The LT3759 features soft-start and frequency foldback
functions to limit inductor current during start-up and
output short-circuit. A window comparator on the FBX pin
reports via the PGOOD pin, providing output voltage status
indication. The device is available in a 12-Lead exposed
pad MSOP package.
Efficiency vs Output Current
OUTPUT CURRENT (A)
0
EFFICIENCY (%)
90
95
100
1.5 2.5
3759 TA01b
85
0.5 1 2
80
75
VIN = 12V
LT3759
VIN
VIN
2.5V TO
36V CIN
4.7µF
×4
41.2k
200kHz
4.7µF ×2
GATE
SENSE
DRIVE
FBX
GND INTVCC
EN/UVLO
PGOOD
SYNC
TIE TO GND
IF NOT USED
RT
SS
VC
L1A
L1B
105k
118k
0.1µF 7.5k
22nF
105K
5mΩ
100k
4.7µF
VOUT
12V
0.5A, 2.5V ≤ VIN ≤ 8V
2A, 8V < VIN ≤ 36V
3759 TA01a
COUT2
47µF
×4
M1
15.8K
+
COUT1
10µF
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PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
VIN ............................................................................42V
EN/UVLO (Note 2) ..................................................... 42V
DRIVE .......................................................................42V
PGOOD ......................................................................42V
INTVCC ........................................................................8V
GATE .................................................................. (Note 3)
SYNC ..........................................................................8V
VC, SS ......................................................................... 3V
(Note 1)
1
2
3
4
5
6
VC
FBX
SS
RT
SYNC
PGOOD
12
11
10
9
8
7
EN/UVLO
VIN
DRIVE
INTVCC
GATE
SENSE
TOP VIEW
MSE PACKAGE
12-LEAD PLASTIC MSOP
13
GND
θJA = 35°C/W TO 40°C/W
EXPOSED PAD (PIN 13) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3759EMSE#PBF LT3759EMSE#TRPBF 3759 12-Lead Plastic MSOP –40°C to 125°C
LT3759IMSE#PBF LT3759IMSE#TRPBF 3759 12-Lead Plastic MSOP –40°C to 125°C
LT3759HMSE#PBF LT3759HMSE#TRPBF 3759 12-Lead Plastic MSOP –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container. Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
RT ............................................................................1.5V
SENSE .................................................................... ±0.3V
FBX ................................................................. –3V to 3V
Operating Junction Temperature Range (Note 4)
LT3759E/LT3759I .............................. –40°C to 125°C
LT3759H ............................................ –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
LT3 759
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ELECTRICAL CHARACTERISTICS
PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Operating Voltage l1.6 42 V
VIN Shutdown IQEN/UVLO < 0.4V
EN/UVLO = 1.15V 0.1 1
6µA
µA
VIN Operating IQ350 450 µA
DRIVE Shutdown Quiescent Current EN/UVLO < 0.4V
EN/UVLO = 1.15V 0.1
0.1 1
2µA
µA
DRIVE Quiescent Current (Not Switching) RT = 27.4kΩ, DRIVE = 6V 2.0 2.5 mA
SENSE Current Limit Threshold l46 50 54 mV
SENSE Input Bias Current Current Out of Pin –55 µA
Error Amplifier
FBX Regulation Voltage (VFBX(REG)) FBX > 0V
FBX < 0V
l
l
1.580
–0.815 1.6
–0.80 1.620
–0.785 V
V
FBX Pin Input Current FBX = 1.6V
FBX = –0.8V
–10 60 120
10 nA
nA
Transconductance gm (ΔI2/ΔVFBX) FBX = VFBX(REG) 240 µs
VC Output Impedance 5MΩ
FBX Line Regulation [ΔVFBX(REG)/(ΔVIN • VFBX(REG))] 1.6V < VIN < 42V, FBX >0
1.6V < VIN < 42V, FBX <0 0.02
0.02 0.05
0.05 %/V
%/V
VC Current Mode Gain (ΔVVC/ΔVSENSE) 5 V/V
VC Source Current FBX = 0V, VC = 1.3V –13 µA
VC Sink Current FBX = 1.7V, VC = 1.3V
FBX = –0.85V, VC = 1.3V 13
10 µA
µA
Oscillator
Switching Frequency RT = 27.4k to GND, VFBX = 1.6V
RT = 86.6k to GND, VFBX = 1.6V
RT = 6.81k to GND, VFBX = 1.6V
270 300
100
1000
330 kHz
kHz
kHz
RT Voltage FBX = 1.6V, –0.8V 1.2 V
GATE Minimum Off-Time 170 200 ns
GATE Minimum On-Time 170 200 ns
SYNC Input Low l0.4 V
SYNC Input High l1.5 V
SS Pull-Up Current SS = 0V, Current Out of Pin l–14 –10.5 –7 µA
Low Dropout Regulators (DRIVE LDO and VIN LDO)
DRIVE LDO Regulation Voltage DRIVE = 6V l4.6 4.75 4.9 V
VIN LDO Regulation Voltage DRIVE = 0V l3.6 3.75 3.9 V
DRIVE LDO Current Limit INTVCC = 4V 60 mA
VIN LDO Current Limit DRIVE = 0V, INTVCC = 3V 60 mA
DRIVE LDO Load Regulation (ΔVINTVCC/VINTVCC) 0 < IINTVCC < 20mA, DRIVE = 6V –1 –0.6 %
VIN LDO Load Regulation (ΔVINTVCC/VINTVCC) DRIVE = 0V, 0 < IINTVCC < 20mA –1 –0.6 %
DRIVE LDO Line Regulation [ΔVINTVCC/(VINTVCC • ΔVIN)] 1.6V < VIN < 42V, DRIVE = 6V 0.03 0.07 %/V
VIN LDO Line Regulation [ΔVINTVCC/(VINTVCC • ΔVIN)] DRIVE = 0V, 5V < VIN < 42V 0.03 0.07 %/V
DRIVE LDO Dropout Voltage (VDRIVE – VINTVcc) DRIVE = 4V, IINTVCC = 20mA l190 400 mV
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted.
LT3 759
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PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN LDO Dropout Voltage (VIN – VINTVcc) VIN = 3V, DRIVE = 0V,
IINTVCC = 20mA
l190 400 mV
INTVCC Undervoltage Lockout Threshold Falling 1.3 1.45 V
INTVCC Current in Shutdown EN/UVLO = 0V 22 µA
Logic
EN/UVLO Threshold Voltage Falling l1.17 1.22 1.27 V
EN/UVLO Rising Hysteresis 20 mV
EN/UVLO Input Low Voltage IVIN < 1μA 0.4 V
EN/UVLO Pin Bias Current Low EN/UVLO = 1.15V 1.8 2.2 2.6 µA
EN/UVLO Pin Bias Current High EN/UVLO = 1.30V 10 100 nA
FBX Power Good Threshold Voltage FBX > 0V, PGOOD Falling
FBX < 0V, PGOOD Falling VFBX(REG) – 0.08
VFBX(REG) + 0.04 V
V
FBX Overvoltage Threshold FBX > 0V, PGOOD Rising
FBX < 0V, PGOOD Rising VFBX(REG) + 0.12
VFBX(REG) – 0.06 V
V
PGOOD Output Low (VOL) IPGOOD = 250µA 210 300 mV
PGOOD Leakage Current PGOOD = 42V 1 µA
INTVCC Minimum Voltage to Enable PGOOD Function l2.4 2.7 3.0 V
INTVCC Minimum Voltage to Enable SYNC Function l2.4 2.7 3.0 V
NMOS Gate Drivers
GATE Output Rise Time (TR) CL = 3300pF 20 ns
GATE Output Fall Time (TF) CL = 3300pF 20 ns
GATE Output Low (VOL)0.05 V
GATE Output High (VOH)INTVCC – 0.05 V
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: For VIN below 4V, the EN/UVLO pin must not exceed VIN for proper
operation.
Note 3: This pin is for switching purposes. Do not tie directly to a supply.
Note 4: The LT3759E is guaranteed to meet performance specifications
from the 0°C to 125°C operating junction temperature range.
Specifications over the –40°C to 125°C operating junction temperature
range are assured by design, characterization and correlation with
statistical process controls. The LT3759I is guaranteed over the full
–40°C to 125°C operating junction temperature range. The LT3759H is
guaranteed over the full –40°C to 150°C operating junction temperature
range. High junction temperatures degrade operating lifetimes. Operating
lifetime is derated at junction temperatures greater than 125°C.
Note 5: The LT3759 is tested in a feedback loop which servos VFBX to the
reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V.
Note 6: Rise and fall times are measured at 10% and 90% levels.
LT3 759
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LT3759
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TYPICAL PERFORMANCE CHARACTERISTICS
Dynamic Quiescent Current
vs Switching Frequency RT vs Switching Frequency
Normalized Switching Frequency
vs FBX Voltage
Switching Frequency
vs Temperature
SENSE Current Limit Threshold
vs Temperature
SENSE Current Limit Threshold
vs Duty Cycle
FBX Positive Regulation Voltage
vs Temperature
FBX Negative Regulation Voltage
vs Temperature
Quiescent Current
vs Temperature
SWITCHING FREQUENCY (kHz)
0
IQ (mA)
15
20
25
600 1000
3759 G04
10
200 400 800
5
0
IQ (VIN)
IQ (DRIVE)
CL = 3300pF, DRIVE = 6V
SWITCHING FREQUENCY (kHz)
0
RT (k)
60
50
80
70
100
90
600 1000
3759 G05
40
30
200100 400 800
700
300 500 900
20
10
0
FBX VOLTAGE (V)
–0.8
NORMALIZED FREQUENCY (%)
80
60
120
100
1.6
3759 G06
40
–0.4 0.8
0 0.4 1.2
20
0
TEMPERATURE (°C)
–75
FBX REGULATION VOLTAGE (V)
1.61
1.62
0 150
3759 G01
1.60
–50 –25 25 50 75 100 125
1.59
1.58
TEMPERATURE (°C)
–75
FBX REGULATION VOLTAGE (V)
–0.79
–0.78
0 150
3759 G02
–0.80
–50 –25 25 50 75 100 125
–0.81
–0.82
TEMPERATURE (°C)
–75
IQ (mA)
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
00 150
3759 G03
–50 –25 25 50 75 100 125
IQ (DRIVE)
IQ (VIN)
VIN = 12V
DRIVE = 6V
TEMPERATURE (°C)
–75
SENSE THRESHOLD (mV)
53
52
51
50
49
48
47 0 150
3759 G08
–50 –25 25 50 75 100 125
DUTY CYCLE (%)
0
SENSE THRESHOLD (mV)
50
48
51
53
52
100
3759 G09
49
20 60
40 80
47
TEMPERATURE (°C)
–75
SWITCHING FREQUENCY (kHz)
350
325
300
275
250 0 150
3759 G07
–50 –25 25 50 75 100 125
RT = 27.4k
TA = 25°C, unless otherwise noted.
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TYPICAL PERFORMANCE CHARACTERISTICS
INTVCC vs Temperature INTVCC Load Regulation INTVCC Line Regulation
INTVCC Dropout Voltage
vs Current, Temperature
Gate Driver Rise and Fall Time
vs CL
Gate Driver Rise and Fall Time
vs INTVCC
EN/UVLO Threshold
vs Temperature
GATE Minimum On- and Off-Times
vs Temperature
EN/UVLO Hysteresis Current
vs Temperature
CL (nF)
0
TIME (ns)
70
60
50
40
30
20
1512
3759 G17
10
6
39
0
RISE TIME
FALL TIME
INTVCC = 4.75V
INTCCC (V)
2
TIME (ns)
25
20
15
10
5
54 4.5
3759 G18
3
2.5 3.5
0
RISE TIME
FALL TIME
CL = 3300pF
TEMPERATURE (°C)
–75
EN/UVLO VOLTAGE (V)
1.27
1.25
1.23
1.21
1.19
1.17 0 150
3759 G10
–50 –25 25 50 75 100 125
EN/UVLO RISING
EN/UVLO FALLING
TEMPERATURE (°C)
–75
EN/UVLO (µA)
2.4
2.2
2.0
1.8
1.6 0 150
3759 G12
–50 –25 25 50 75 100 125
INTVCC LOAD (mA)
0
INTVCC VOLTAGE (V)
4.0
3.5
6.0
5.5
5.0
4.5
25
3759 G14
2.5
3.0
515
10 20
2.0
DRIVE LDO
VIN LDO (DRIVE = 0V)
INTVCC LOAD (mA)
0
DROPOUT VOLTAGE (mV)
200
400
300
25
3759 G16
100
515
10 20
0
VIN = 12V
DRIVE = 4V
150°C
25°C
–55°C
TEMPERATURE (°C)
–75
INTVCC (V)
5.0
4.8
4.6
4.4
4.0
3.8
4.2
3.6 0 150
3759 G13
–50 –25 25 50 75 100 125
DRIVE LDO
VIN LDO
TA = 25°C, unless otherwise noted.
TEMPERATURE (°C)
–75
MINIMUM ON/OFF TIME (ns)
200
190
180
170
160
150
140
130 0 150
3759 G11
–50 –25 25 50 75 100 125
MINIMUM
OFF TIME
MINIMUM
ON TIME
VIN (V)
0
INTVCC VOLTAGE (V)
5.0
4.5
4.0
4535 40
3759 G15
3.5
515
10 20 3025
3.0
DRIVE LDO
VIN LDO
LT3 759
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PIN FUNCTIONS
DRIVE: DRIVE LDO Supply Pin. This pin can be connected
to either VIN or a quasi-regulated voltage supply such as
a DC converter output. This pin must be bypassed with
a minimum of 1µF capacitor placed close to the pin. Tie
this pin to VIN if not used.
EN/UVLO: Shutdown and Undervoltage Detect Pin. An
accurate 1.22V (nominal) falling threshold with externally
programmable hysteresis detects when power is okay to
enable switching. Rising hysteresis is generated by the
external resistor divider and an accurate internal 2.2μA
pull-down current. An undervoltage condition resets soft-
start. Tie to 0.4V, or less, to disable the device and reduce
VIN quiescent current below 1μA.
FBX: Voltage Regulation Feedback Pin for Positive or
Negative Outputs. Connect this pin to a resistor divider
between the output and GND. FBX is the input of two error
amplifiers—one configured to regulate a positive output;
the other, a negative output. Depending upon topology
selected, switching causes the output to ramp positive or
negative. The appropriate amplifier takes control while the
other becomes inactive. Additionally FBX is input for two
window comparators that indicate through the PGOOD
pin when the output is within 5% of the regulation volt-
ages. FBX also modulates the switching frequency during
start-up and fault conditions when FBX is close to GND.
GATE: N-Channel FET Gate Driver Output. Switches
between INTVCC and GND. Driven to GND when IC is shut
down, during thermal lockout or when INTVCC is below
undervoltage threshold.
GND: Exposed Pad. Solder the exposed pad directly to
ground plane.
INTVCC: Regulated Supply for Internal Loads and Gate
Driver. Regulated to 4.75V if powered from DRIVE or
regulated to 3.75V if powered from VIN. The INTVCC pin
must be bypassed with a minimum of 4.7µF capacitor
placed close to the pin.
PGOOD: Output Ready Status Pin. An open-collector pull
down on PGOOD asserts when INTVCC is greater than
2.7V and the FBX voltage is within 5% (80mV if VFBX =
1.6V or 40mV if VFBX = –0.8V) of the regulation voltage.
RT: Switching Frequency Adjustment Pin. Set the frequency
using a resistor to GND. Do not leave the RT pin open.
SENSE: The Current Sense Input for the Control Loop.
Kelvin connect this pin to the positive terminal of the
switch current sense resistor in the source of the N-FET.
The negative terminal of the current sense resistor should
be connected to GND plane close to the IC.
SS: Soft-Start Pin. This pin modulates compensation pin
voltage (VC) clamp. The soft-start interval is set with an
external capacitor. The pin has a 10µA (typical) pull-up
current source to an internal 2.5V rail. The soft-start pin
is reset to GND by an EN/UVLO undervoltage condition,
an INTVCC undervoltage condition or an internal thermal
lockout.
SYNC: Frequency Synchronization Pin. Used to synchronize
the internal oscillator to an outside clock. If this feature is
used, an RT resistor should be chosen to program a switch-
ing frequency 20% slower than SYNC pulse frequency.
Tie the SYNC pin to GND if this feature is not used. This
signal is ignored during FB frequency foldback or when
INTVCC is less than 2.7V.
VC: Error Amplifier Compensation Pin. Used to stabilize
the voltage loop with an external RC network.
VIN: Supply Pin for Internal Leads and the VIN LDO
Regulator of INTVCC. Must be locally bypassed with a
minimum of 1µF capacitor placed close to this pin.
LT3 759
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BLOCK DIAGRAM
M1
1.22V
1.2V
2.5V
CIN
CVCC
INTVCC
DRIVEVIN
RSENSE
VISENSE
+
IS1
2µA
10
9
8
1
12 EN/UVLO
BANDGAP
REFERENCE
TSD
~165˚C
A10
Q3
VC
VC
BG_LOW
UVLO
IS2
10µA
IS3
CC1
CC2
RC
DRIVER
SLOPE SENSE
GND
GATE
50mV
SR1
+
–
RAMP
GENERATOR
+
–
R Q
S
2.5V
RT
RT
SS
CSS
SYNC
FREQ
FOLDBACK
1.25V
FBX
PGOOD
FBX
Q4
1.6V
–0.8V
+
–
+
–
2
6
3 5 4
+
–
+
–
7
13
RAMP
PWM
COMPARATOR
FREQUENCY
FOLDBACK
100kHz ~ 1MHz
OSCILLATOR
R1
R2
L2
FBX
D1
CDC
VOUT
COUT2
COUT1
•+
3759 F01
A1
A2
1.72V
–0.86V
+
–
+
–
A11
A12
+
–
A3
1.25V
FREQ
PROG
–
+
+Q1
A4
A5
A6
G5
G6
A7
Q2
G4
R3R4
VIN
11
INTERNAL BIAS
GENERATOR
DRIVE LDO
CURRENT
LIMIT
INTERNAL BIAS
CURRENT
LIMIT
VIN LDO
A8
+
–
G8
1.52V
–0.76V
+
–
+
–
A13
A14 G7
2.7V
A15
+
–
G2
G1
•
L1
BG
Figure 1. LT3759 Block Diagram Working as a SEPIC Converter
LT3 759
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APPLICATIONS INFORMATION
Main Control Loop
The LT3759 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation.
Operation can be best understood by referring to the Block
Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1) and
turns on the external power MOSFET switch M1 through
driver G2. The switch current flows through the external
current sensing resistor RSENSE and generates a voltage
proportional to the switch current. This current sense
voltage VISENSE (amplified by A5) is added to a stabilizing
slope compensation ramp and the resulting sum (SLOPE)
is fed into the positive terminal of the PWM comparator A7.
When SLOPE exceeds the level at the negative input of A7
(VC pin), SR1 is reset, turning off the power switch. The
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
The LT3759 has a switch current limit function. The current
sense voltage is input to the current limit comparator A6.
If the SENSE pin voltage is higher than the sense current
limit threshold VSENSE(MAX) (50mV, typical), A6 will reset
SR1 and turn off M1 immediately.
The LT3759 is capable of generating either positive or nega-
tive output voltage with a single FBX pin. It can be configured
as a boost or SEPIC converter to generate positive output
voltage, or as an inverting converter to generate negative
output voltage. When configured as a SEPIC converter, as
shown in Figure 1, the FBX pin is pulled up to the internal bias
voltage of 1.6V by a voltage divider (R1 and R2) connected
from VOUT to GND. Comparator A2 becomes inactive and
comparator A1 performs the inverting amplification from
FBX to VC. When the LT3759 is in an inverting configuration,
the FBX pin is pulled down to –0.8V by a voltage divider
connected from VOUT to GND. Comparator A1 becomes
inactive and comparator A2 performs the noninverting
amplification from FBX to VC.
The LT3759 has overvoltage protection functions to protect
the converter from excessive output voltage overshoot
during start-up or recovery from a short-circuit condition.
An overvoltage comparator A11 (with 40mV hysteresis)
senses when the FBX pin voltage exceeds the positive
regulated voltage (1.6V) by 7.5% and turns off M1.
Similarly, an overvoltage comparator A12 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
negative regulated voltage (–0.8V) by 7.5% and turns
off M1. Both reset pulses are sent to the main RS latch
(SR1) through G6 and G5. The external power MOSFET
switch M1 is actively held off for the duration of an output
overvoltage condition.
Programming Turn-On and Turn-Off Thresholds with
EN/UVLO Pin
The EN/UVLO pin controls whether the LT3759 is enabled
or is in shutdown state. A micropower 1.22V reference, a
comparator A10 and controllable current source IS1 allow
the user to accurately program the supply voltage at which
the IC turns on and off. The falling value can be accurately
set by the resistor dividers R3 and R4. When EN/UVLO
is above 0.7V, and below the 1.22V threshold, the small
pull-down current source IS1 (typical 2µA) is active.
The purpose of this current is to allow the user to program
the rising hysteresis. The Block Diagram of the comparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
VVIN(FALLING) =1.22•(R3+R4)
R4
VVIN(RISING) =2µA •R3+VIN(FALLING)
For applications where the EN/UVLO pin is only used as
a logic input, the EN/UVLO pin can be connected directly
to the input voltage VIN for always-on operation.
INTVCC Low Dropout Voltage Regulators
The LT3759 features two internal low dropout (LDO) volt-
age regulators (VIN LDO and DRIVE LDO) powered from
different supplies (VIN and DRIVE respectively). Both LDO’s
regulate the internal INTVCC supply which powers the gate
driver and the internal loads, as shown in Figure 1. Both
regulators are designed so that current does not flow from
INTVCC to the LDO input under a reverse bias condition.
DRIVE LDO regulates the INTVCC to 4.75V, while VIN LDO
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regulates the INTVCC to 3.75V. VIN LDO is turned off when
the INTVCC voltage is greater than 3.75V (typical). Both
LDO’s can be turned off if the INTVCC pin is driven by a
supply of 4.75V or higher but less than 8V (the INTVCC
maximum voltage rating is 8V). A table of the LDO sup-
ply and output voltage combination is shown in Table 1.
Table 1. LDO’s Supply and Output Voltage Combination (Assuming
That the LDO Dropout Voltage is 0.15V)
SUPPLY VOLTAGES LDO OUTPUT LDO STATUS
(Note 7)
VIN DRIVE INTVCC
VIN ≤ 3.9V VDRIVE < VIN VIN – 0.15V #1 Is ON
VDRIVE = VIN VIN – 0.15V #1 #2 are ON
VIN < VDRIVE < 4.9V VDRIVE – 0.15V #2 Is ON
4.9V ≤ VDRIVE ≤ 42V 4.75V #2 Is ON
3.9V < VIN ≤ 42V VDRIVE < 3.9V 3.75V #1 Is ON
VDRIVE = 3.9V 3.75V #1 #2 are ON
3.9V < VDRIVE < 4.9V VDRIVE – 0.15V #2 Is ON
4.9V ≤ VDRIVE ≤ 42V 4.75V #2 Is ON
Note 7: #1 is VIN LDO and #2 is DRIVE LDO
The DRIVE pin provides flexibility to power the gate driver
and the internal loads from a supply that is available only
when the switcher is enabled and running. If not used, the
DRIVE pin should be tied to VIN.
The INTVCC pin must be bypassed to ground immediately
adjacent to the INTVCC pin with a minimum of 4.7µF ceramic
capacitor. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate driver.
If a low input voltage operation is expected (VIN is 3V or
less), low threshold MOSFETs should be used. The LT3759
contains an undervoltage lockout comparator A8 for the
internal INTVCC supply. The INTVCC undervoltage (UV)
threshold is 1.3V (typical), with 100mV hysteresis, to
ensure that the MOSFETs have sufficient gate drive voltage
before turning on. The logic circuitry within the LT3759
is also powered from the internal INTVCC supply. When
INTVCC is below the UV threshold, the GATE pin will be
forced to GND and the soft-start operation will be triggered.
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
The on-chip power dissipation can be a significant con-
cern when a large power MOSFET is being driven at a
high frequency and the VIN voltage is high. It is important
to limit the power dissipation with proper selection of a
MOSFET and/or an operating frequency so the LT3759
does not exceed its maximum junction temperature rating.
The junction temperature TJ can be estimated using the
following equations:
T
J
=T
A
+P
IC
•θ
JA
TA = ambient temperature
θJA = junction-to-ambient thermal resistance
PIC = IC power consumption = VIN • (IQ + IDRIVE)
(Assume the DRIVE pin is connected to VIN Supply)
IQ = VIN operation IQ = 1.8mA
IDRIVE = average gate drive current = f • QG
f = switching frequency
QG = power MOSFET total gate charge
The LT3759 uses packages with an exposed pad for en-
hanced thermal conduction. With proper soldering to the
exposed pad on the underside of the package and a full
copper plane underneath the device, thermal resistance
(θJA) will be about 40°C/W for the MSE package.
The LT3759 has an internal INTVCC IDRIVE current limit
function to protect the IC from excessive on-chip power
dissipation. If IDRIVE reaches the current limit, INTVCC
voltage will fall and may trigger the soft-start.
There is a trade-off between the operating frequency and
the size of the power MOSFET (QG) in order to maintain
a reliable IC junction temperature. Prior to lowering the
operating frequency, however, be sure to check with
power MOSFET manufacturers for their most recent low
QG, low RDS(ON) devices. Power MOSFET manufacturing
technologies are continually improving, with newer and
better performance devices being introduced almost yearly.
Operating Frequency and Synchronization
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency
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operation improves efficiency by reducing gate drive cur-
rent and MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger loop
inductor. Switching frequency also has implications for
loop compensation. The LT3759 uses a constant-frequency
architecture that can be programmed over a 100kHz to
1MHz range with a single external resistor from the RT pin
to ground, as shown in Figure 1. The RT pin must have
an external resistor to GND for proper operation of the
LT3759. A table for selecting the value of RT for a given
operating frequency is shown in Table 2.
Table 2. Timing Resistor (RT) Value
OSCILLATOR FREQUENCY (kHz) RT (kΩ)
100 86.6
200 41.2
300 27.4
400 21.0
500 16.5
600 13.7
700 11.5
800 9.76
900 8.45
1000 6.81
The switching frequency of the LT3759 can be synchronized
to the positive edge of an external clock source. By provid-
ing a digital clock signal into the SYNC pin, the LT3759 will
operate at the SYNC clock frequency. If this feature is used,
an RT resistor should be chosen to program a switching
frequency 20% slower than SYNC pulse frequency. The
SYNC pulse should have a minimum pulse width of 200ns.
Tie the SYNC pin to GND if this feature is not used.
Duty Cycle Consideration
Switching duty cycle is a key variable defining converter
operation. As such, its limits must be considered. Minimum
on-time is the smallest time duration that the LT3759 is
capable of turning on the power MOSFET. This time is
generally about 170ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3759 keeps the power switch off for at least
170ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
The output voltage (VOUT) is set by a resistor divider, as
shown in Figure 1. The positive VOUT and negative VOUT
are set by the following equations:
VOUT(POSITIVE) =1.6V •1+R2
R1
VOUT(NEGATIVE) =–0.8V •1+R2
R1
The resistors R1 and R2 are typically chosen so that the
error caused by the current flowing into the FBX pin dur-
ing normal operation is less than 1% (this translates to a
maximum value of R1 at about 158k).
Soft-Start
The LT3759 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since VOUT is far from its final value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
LT3759 addresses this mechanism with the SS pin. As
shown in Figure 1, the SS pin reduces the power MOSFET
current by pulling down the VC pin through Q2. In this
way the SS allows the output capacitor to charge gradually
toward its final value while limiting the start-up peak
currents.
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Besides start-up, soft-start can also be triggered by
INTVCC undervoltage lockout and/or thermal lockout, which
causes the LT3759 to stop switching immediately. The SS
pin will be discharged by Q3. When all faults are cleared
and the SS pin has been discharged below 0.2V, a 10µA
current source IS2 starts charging the SS pin, initiating a
soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
TSS =CSS •1.25V
10µA
FBX Frequency Foldback
When VOUT is very low during start-up or a short-circuit
fault on the output, the switching regulator must operate
at low duty cycles to maintain the power switch current
within the current limit range, since the inductor current
decay rate is very low during switch off time. The minimum
on-time limitation may prevent the switcher from attaining
a sufficiently low duty cycle at the programmed switch-
ing frequency. So, the switch current will keep increasing
through each switch cycle, exceeding the programmed
current limit. To prevent the switch peak currents from
exceeding the programmed value, the LT3759 contains
a frequency foldback function to reduce the switching
frequency when the FBX voltage is low (see the Normal-
ized Switching Frequency vs FBX graph in the Typical
Performance Characteristics section).
Some frequency foldback waveforms are shown in the
Typical Applications section. The frequency foldback func-
tion prevents IL from exceeding the programmed limits
because of the minimum on-time.
During frequency foldback, external clock synchronization
is disabled to allow the frequency reducing operation to
function properly.
Thermal Lockout
If the LT3759 die temperature reaches 165°C (typical),
the part will go into thermal lockout. The power switch
will be turned off. A soft-start operation will be triggered.
The part will be enabled again when the die temperature
has dropped by 5°C (nominal).
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3759 uses current mode control to
regulate the output which simplifies loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3759, a series resistor-capacitor
network is usually connected from the VC pin to GND.
Figure 1 shows the typical VC compensation network. For
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of
5k to 50k. A small capacitor is often connected in paral-
lel with the RC compensation network to attenuate the
VC voltage ripple induced from the output voltage ripple
through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.
SENSE Pin Programming
For control and protection, the LT3759 measures the
power MOSFET current by using a sense resistor (RSENSE)
between GND and the MOSFET source. Figure 2 shows a
typical wave-form of the sense voltage (VSENSE) across the
sense resistor. It is important to use Kelvin traces between
the SENSE pin and RSENSE, and to place the IC GND as
close as possible to the GND terminal of the RSENSE for
proper operation.
Figure 2. The Sense Voltage During a Switching Cycle
APPLICATIONS INFORMATION
3759 F02
VSENSE(PEAK)
ΔVSENSE = χ • VSENSE(MAX)
VSENSE
t
DTS
VSENSE(MAX)
TS
AVSENSE
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Due to the current limit function of the SENSE pin, RSENSE
should be selected to guarantee that the peak current sense
voltage VSENSE(PEAK) during steady state normal opera-
tion is lower than the SENSE current limit threshold (see
the Electrical Characteristics table). Given a 20% margin,
VSENSE(PEAK) is set to be 40mV. Then, the maximum switch
ripple current percentage can be calculated using the fol-
lowing equation:
c =
D
VSENSE
40mV -0.5 •DVSENSE
χ is used in subsequent design examples to calculate
inductor value. ΔVSENSE is the ripple voltage across RSENSE.
The LT3759 has internal slope compensation to stabilize
the control loop against sub-harmonic oscillation. When
the LT3759 operates at a high duty cycle in continuous
conduction mode, the SENSE voltage ripple ΔVSENSE (re-
fer to Figure 2) needs to be limited to ensure the internal
slope compensation is sufficient to stabilize the control
loop. Figure 3 shows the maximum allowed ΔVSENSE over
the duty cycle. It is recommended to check and ensure
ΔVSENSE is below the curve at the highest duty cycle. Figure 4. The RC Filter on SENSE pin
APPLICATIONS INFORMATION
The LT3759 switching controller incorporates 100ns timing
interval to blank the ringing on the current sense signal
immediately after M1 is turned on. This ringing is caused
by the parasitic inductance and capacitance of the PCB
trace, the sense resistor, the diode, and the MOSFET. The
100ns timing interval is adequate for most of the LT3759
applications. In the applications that have very large and
long ringing on the current sense signal, a small RC filter
can be added to filter out the excess ringing. Figure 4
shows the RC filter on SENSE pin. It is usually sufficient
to choose 22Ω for RFLT and 2.2nF to 10nF for CF LT . Keep
RFLT’s resistance low. Remember that there is 50µA (typi-
cal) flowing out of the SENSE pin. Adding RFLT will affect
the SENSE current limit threshold:
V
SENSE _ILIM
=50mV −50µA •R
FLT
CFLT
3759 F04
LT3759 RFLT
RSENSE
M1
SENSE
GATE
GND
Figure 3. The Maximum Allowed SENSE Voltage Ripple vs
Duty Cycle
DUTY CYCLE
0
MAXIMUM ∆VSENSE (mV)
40
30
60
50
1
3759 F03
20
0.1 0.5 0.6 0.7
0.2 0.3 0.4 0.8 0.9
10
0
APPLICATION CIRCUITS
The LT3759 can be configured as different topologies.
The design procedure for component selection differs
somewhat between these topologies. The first topology
to be analyzed will be the boost converter, followed by the
flyback SEPIC and inverting converters.
Boost Converter: Switch Duty Cycle and Frequency
The LT3759 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
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The selection of switching frequency is the starting point.
The maximum frequency that can be used is based on the
maximum duty cycle. The conversion ratio as a function
of duty cycle is:
VOUT
VIN =1
1−D
in continuous conduction mode (CCM). The equations
that follow assume CCM operation.
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT) and the input voltage (VIN). The maximum
duty cycle (DMAX) occurs when the converter has the
minimum input voltage:
DMAX =VOUT −VIN(MIN)
VOUT
The alternative to CCM, discontinuous conduction mode
(DCM) is not limited by duty cycle to provide high con-
version ratios at a given frequency. The price one pays
is reduced efficiency and substantially higher switching
current.
Boost Converter: Inductor and Sense Resistor Selection
For the boost topology, the maximum average inductor
current is:
IL(MAX) =IO(MAX) •1
1−DMAX
Then, the ripple current can be calculated by:
DIL=c•IL(MAX) =c•IO(MAX) •1
1-DMAX
The constant χ in the preceding equation represents the
percentage peak-to-peak ripple current in the inductor,
relative to IL(MAX).
The inductor ripple current has a direct effect on the choice
of inductor value. Choosing smaller values of ΔIL requires
large inductances and reduces the current loop gain (the
converter will approach voltage mode). Accepting larger
values of ΔIL provides fast transient response and allows
the use of low inductances, but results in higher input
current ripple and greater core losses. It is recommended
that χ falls within the range of 0.2 to 0.6.
The peak and RMS inductor current are:
IL(PEAK) =IL(MAX) •1+χ
2
IL(RMS) =IL(MAX) •1+χ2
12
The inductor used with the LT3759 should have a saturation
current rating appropriate to the maximum switch current
selected with the RSENSE resistor. Choose an inductor value
based on operating frequency, input and output voltage
to provide a current mode ramp on SENSE during the
switch on-time of approximately 10mV magnitude. The
following equation is useful to estimate the inductor value
for continuous conduction mode operation:
L=RSENSE •VIN(MIN)
0.01V •fOSC
•DMAX
Set the sense voltage at IL(PEAK) to be the minimum of the
SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
RSENSE =40mV
IL(PEAK)
Boost Converter: Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-source voltage rating (VDS), the threshold voltage
(VGS(TH)), the on-resistance (RDS(ON)), the gate to source
and gate to drain charges (QGS and QGD), the maximum
drain current (ID(MAX)) and the MOSFET’s thermal resis-
tances (RθJC and RθJA).
The power MOSFET will see full output voltage, plus a
diode forward voltage, and any additional ringing across
its drain-to-source during its off-time. It is recommended
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to choose a MOSFET whose BVDSS is higher than VOUT
by a safety margin (a 10V safety margin is usually
sufficient).
The power dissipated by the MOSFET in a boost
converter is:
PFET =I2L(MAX) •RDS(ON) •DMAX
+V2OUT •IL(MAX) •CRSS •f
1A
The first term in the preceding equation represents the
conduction losses in the devices, and the second term, the
switching loss. CRSS is the reverse transfer capacitance,
which is usually specified in the MOSFET characteristics.
For maximum efficiency, RDS(ON) and CRSS should be
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
TJ=TA•PF ET •θJA
=TA+PFET •(θJ C +θCA)
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to:
ID(PEAK) =IL(PEAK) =1+χ
2
•IL(MAX)
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT by a safety margin (a 10V
safety margin is usually sufficient).
The power dissipated by the diode is:
P
D
=I
O(MAX)
•V
D
and the diode junction temperature is:
T
J=
T
A•
P
D•
R
θJA
The RθJA to be used in this equation normally includes the
RθJC for the device plus the thermal resistance from the
board to the ambient temperature in the enclosure. TJ must
not exceed the diode maximum junction temperature rating.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
these three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform for a typical boost converter is
illustrated in Figure 5.
The choice of component(s) begins with the maximum
APPLICATIONS INFORMATION
Figure 5. The Output Ripple Waveform of a Boost Converter
VOUT
(AC)
tON
∆VESR
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
∆VCOUT
3759 F05
tOFF
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ΔVESR and charging/discharging
ΔVCOUT. For the purpose of simplicity, we will choose
2% for the maximum output ripple, to be divided equally
between ΔVESR and ΔVCOUT. This percentage ripple will
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change, depending on the requirements of the applica-
tion, and the following equations can easily be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the fol-
lowing equation:
ESRCOUT ≤0.01•VOUT
ID(PEAK)
For the bulk C component, which also contributes 1% to
the total ripple:
COUT ≥IO(MAX)
0.01•VOUT •f
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 5. The RMS ripple
current rating of the output capacitor can be determined
using the following equation:
IRMS(COUT) ≥IO(MAX) •DMAX
1−DMAX
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering and has
the required RMS current rating. Additional ceramic capaci-
tors in parallel are commonly used to reduce the effect of
parasitic inductance in the output capacitor, which reduces
high frequency switching noise on the converter output.
Boost Converter: Input Capacitor Selection
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 10µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
The RMS input capacitor ripple current for a boost
converter is:
IRMS(CIN) =0.3 •DIL
FLYBACK CONVERTER APPLICATIONS
The LT3759 can be configured as a flyback converter for the
applications where the converters have multiple outputs,
high output voltages or isolated outputs. Figure 6 shows
a simplified flyback converter.
The flyback converter has a very low parts count for mul-
tiple outputs, and with prudent selection of turns ratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
the high peak currents, high peak voltages and consequent
power loss. The flyback converter is commonly used for
an output power of less than 50W.
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower efficiency. In the high output voltage
applications, the flyback converters can be designed
to operate in discontinuous mode to avoid using large
transformers.
APPLICATIONS INFORMATION
Figure 6. A Simplified Flyback Converter
RSENSE
NP:NS
VIN
CIN CSN
VSN LP
D
SUGGESTED
RCD SNUBBER
ID
ISW
VDS
3759 F06
GATE
GND
LT3759
SENSE
LS
M
+
–
+
–
RSN
DSN
–
+
+
COUT
+
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Flyback Converter: Switch Duty Cycle and Turns Ratio
The flyback converter conversion ratio in the continuous
mode operation is:
VOUT
VIN =NS
NP
•D
1−D
where NS/NP is the second to primary turns ratio.
Figure 7 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
period TS, three subintervals occur: DTS, D2TS, D3TS.
During DTS, M is on, and D is reverse-biased. During
D2TS, M is off, and LS is conducting current. Both LP and
LS currents are zero during D3TS.
The flyback converter conversion ratio in the discontinu-
ous mode operation is:
VOUT
VIN =NS
NP
•D
D2
According to the preceding equations, the user has relative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when select-
ing the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
• Lower MOSFET RMS current ISW(RMS), but higher
MOSFET VDS peak voltage
• Lower diode peak reverse voltage, but higher diode
RMS current ID(RMS)
• Higher transformer turns ratio (NP/NS)
The choice,
D
D
+
D2 =1
3
(for discontinuous mode operation with a given D3) gives
the power MOSFET the lowest power stress (the product
of RMS current and peak voltage). However, in the high
output voltage applications, a higher duty cycle may be
adopted to limit the large peak reverse voltage of the
diode. The choice,
D
D
+
D2 =2
3
(for discontinuous mode operation with a given D3) gives
the diode the lowest power stress (the product of RMS
current and peak voltage). An extreme high or low duty
cycle results in high power stress on the MOSFET or diode,
and reduces efficiency. It is recommended to choose a
duty cycle, D, between 20% and 80%.
APPLICATIONS INFORMATION
Figure 7. Waveforms of the Flyback Converter in
Discontinuous Mode Operation
3759 F07
ISW
VDS
ID
t
DTSD2TSD3TS
ISW(MAX)
ID(MAX)
TS
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APPLICATIONS INFORMATION
Flyback Converter: Transformer Design for
Discontinuous Mode Operation
The transformer design for discontinuous mode of opera-
tion is chosen as presented here. According to Figure 7,
the minimum D3 (D3MIN) occurs when the converter
has the minimum VIN and the maximum output power
(POUT). Choose D3MIN to be equal to or higher than 10%
to guarantee the converter is always in discontinuous
mode operation (choosing higher D3 allows the use of low
inductances, but results in a higher switch peak current).
The user can choose a DMAX as the start point. Then, the
maximum average primary currents can be calculated by
the following equation:
ILP(MAX) =ISW(MAX) =POUT(MAX)
DMAX •VIN(MIN) •η
where h is the converter efficiency.
If the flyback converter has multiple outputs, POUT(MAX)
is the sum of all the output power.
The maximum average secondary current is:
ILS(MAX) =ID(MAX) =IOUT(MAX)
D2
where:
D2 = 1 – DMAX – D3
the primary and secondary RMS currents are:
ILP(RMS) =2•ILP(MAX) •DMAX
3
ILS(RMS) =2•ILS(MAX) •D2
3
According to Figure 7, the primary and secondary peak
currents are:
ILP(PEAK) = ISW(PEAK) = 2 • ILP(MAX)
ILS(PEAK) = ID(PEAK) = 2 • ILS(MAX)
The primary and second inductor values of the flyback
converter transformer can be determined using the fol-
lowing equations:
LP=D2MAX •V2IN(MIN) •η
2•POUT(MAX) •fOSC
LS=D22•(VOUT +VD)
2•IOUT(MAX) •fOSC
The primary to second turns ratio is:
NP
NS=LP
LS
Flyback Converter: Snubber Design
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to occur after the MOS-
FET turn-off. This is increasingly prominent at higher load
currents, where more stored energy must be dissipated.
In some cases a snubber circuit will be required to avoid
overvoltage breakdown at the MOSFET’s drain node. There
are different snubber circuits, and Application Note 19 is
a good reference on snubber design. An RCD snubber is
shown in Figure 6.
The snubber resistor value (RSN) can be calculated by the
following equation:
RSN =2•
V2SN −VSN •VOUT •NP
NS
I2SW(PEAK) •LLK •fOSC
where VSN is the snubber capacitor voltage. A smaller
VSN results in a larger snubber loss. A reasonable VSN is
2 to 2.5 times of:
VOUT •NP
NS
LT3 759
L7HEJWEGR 1 9
LT3759
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3759fc
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APPLICATIONS INFORMATION
LLK is the leakage inductance of the primary winding, which
is usually specified in the transformer characteristics. LLK
can be obtained by measuring the primary inductance with
the secondary windings shorted. The snubber capacitor
value (CCN) can be determined using the following equation:
CCN =VSN
ΔVSN •RCN •fOSC
where ΔVSN is the voltage ripple across CCN. A reasonable
ΔVSN is 5% to 10% of VSN. The reverse voltage rating of
DSN should be higher than the sum of VSN and VIN(MAX).
Flyback Converter: Sense Resistor Selection
In a flyback converter, when the power switch is turned
on, the current flowing through the sense resistor
(ISENSE) is:
ISENSE = ILP
Set the sense voltage at ILP(PEAK) to be the minimum of
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
RSENSE =40mV
ILP(PEAK)
Flyback Converter: Power MOSFET Selection
For the flyback configuration, the MOSFET is selected with
a VDC rating high enough to handle the maximum VIN, the
reflected secondary voltage and the voltage spike due to
the leakage inductance. Approximate the required MOSFET
VDC rating using:
BVDSS > VDS(PEAK)
where:
V
DS(PEAK)
=V
IN(MAX)
+V
SN
The power dissipated by the MOSFET in a flyback con-
verter is:
PFET = I2M(RMS) • RDS(ON) + 2 • V2DS(PEAK) • IL(MAX) •
CRSS • f
OSC/1A
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
loss. CRSS is the reverse transfer capacitance, which is
usually specified in the MOSFET characteristics.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
equation:
TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA)
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.
Flyback Converter: Output Diode Selection
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
Approximate the required peak repetitive reverse voltage
rating VRRM using:
VRRM >NS
NP
•VIN(MAX) +VOUT
The power dissipated by the diode is:
PD = IO(MAX) • VD
and the diode junction temperature is:
TJ = TA + PD • RθJA
The RθJA to be used in this equation normally includes the
RθJC for the device, plus the thermal resistance from the
board to the ambient temperature in the enclosure. TJ must
not exceed the diode maximum junction temperature rating.
Flyback Converter: Output Capacitor Selection
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer to
the Boost Converter: Output Capacitor Selection section
for the calculation of COUT and ESRCOUT.
LT3 759
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LT3759
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3759fc
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The RMS ripple current rating of the output capacitors
in discontinuous operation can be determined using the
following equation:
IRMS(COUT),DISCONTINUOUS ≥IO(MAX) •4−(3 •D2)
3•D2
Flyback Converter: Input Capacitor Selection
The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
discontinuous operation can be determined using the
following equation:
IRMS(CIN),DISCONTINUOUS ≥POUT(MAX)
VIN(MIN)•η•4−(3 •DMAX)
3•DMAX
SEPIC CONVERTER APPLICATIONS
The LT3759 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
VOUT +VD
VIN =D
1−D
In continuous conduction mode (CCM).
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT), the input voltage (VIN) and diode forward
voltage (VD).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =
V
OUT
+V
D
VIN(MIN) +VOUT +VD
SEPIC Converter: Inductor and Sense Resistor
Selection
As shown in Figure 1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but can
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
IL1(MAX) =IIN(MAX) =IO(MAX)
D
MAX
1–DMAX
IL2(MAX) =IO(MAX)
In a SEPIC converter, the switch current is equal to IL1 +
IL2 when the power switch is on, therefore, the maximum
average switch current is defined as:
I
SW(MAX)
=I
L1(MAX)
+I
L2(MAX)
=IO(MAX) •1
1–DMAX
and the peak switch current is:
ISW(PEAK) =1+
χ
2
•IO(MAX) •
1
1–DMAX
The constant χ in the preceding equations represents the
percentage peak-to-peak ripple current in the switch, rela-
tive to ISW(MAX), as shown in Figure 8. Then, the switch
ripple current ΔISW can be calculated by:
D
ISW
= c
•ISW(MAX)
APPLICATIONS INFORMATION
LT3 759
050
L7 LJUW 2 1
LT3759
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3759fc
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The inductor ripple currents ΔIL1 and ΔIL2 are identical:
DIL1= DIL2 =0.5 •DISW
By making L1 = L2, and winding them on the same core, the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
L=VIN(MIN)
DISW •fOSC
•DMAX
=RSENSE •VIN(MIN)
0.01V •fOSC
•DMAX
In a SEPIC converter, when the power switch is turned on,
the current flowing through the sense resistor (ISENSE) is
the switch current.
Set the sense voltage at ISENSE(PEAK) to be minimum of
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
RSENSE =40mV
ISW(PEAK)
SEPIC Converter: Power MOSFET Selection
For the SEPIC configuration, choose a MOSFET with a
VDC rating higher than the sum of the output voltage and
input voltage by a safety margin (a 10V safety margin is
usually sufficient).
The power dissipated by the MOSFET in a SEPIC converter
is:
P
FET =I2SW(MAX) •RDS(ON) •DMAX
+(VIN(MIN) +VOUT)2•ISW(MAX)
•CRSS •fOSC
1A
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
loss. CRSS is the reverse transfer capacitance, which is
usually specified in the MOSFET characteristics.
Figure 8. The Switch Current Waveform of a SEPIC Converter
3759 F08
∆ISW = χ • ISW(MAX)
ISW
t
DTS
ISW(MAX)
TS
APPLICATIONS INFORMATION
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
ΔIL requires large inductances and reduces the current
loop gain (the converter will approach voltage mode).
Accepting larger values of ΔIL allows the use of low in-
ductances, but results in higher input current ripple and
greater core losses. It is recommended that χ falls in the
range of 0.2 to 0.4.
Choose an inductor value based on operating frequency,
input and output voltage to provide a current mode ramp
on SENSE during the switch on-time of approximately
10mV magnitude. The inductor value (L1 and L2 are
independent) of the SEPIC converter can be determined
using the following equation:
L1=L2 =
V
IN(MIN)
0.5 •DISW •fOSC
•DMAX
=RSENSE •VIN(MIN)
0.5 •0.01V •fOSC
•DMAX
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 100µH.
LT3 759
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VIN(M|N)
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For maximum efficiency, RDS(ON) and CRSS should be
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
TJ=TA+PFET •θJA
=TA+PFET •(θJC + θCA )
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current, and the peak current is equal to:
ID(PEAK) =1+
χ
2
•IO(MAX) •1
1−DMAX
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT + VIN(MAX) by a safety
margin (a 10V safety margin is usually sufficient).
The power dissipated by the diode is:
P
D
=I
O(MAX)
•V
D
and the diode junction temperature is:
T
J
=T
A
+P
D
•Rθ
JA
The RθJA used in this equation normally includes the RθJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPIC converter are similar to those of the boost converter.
Please refer to the Boost Converter, Output Capacitor
Selection and Boost Converter, Input Capacitor Selection
sections.
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 1) should be rated for the maximum
input voltage:
CDC ≥VIN(MAX)
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) ≥IO(MAX) •VOUT +VD
VIN(MIN)
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
INVERTING CONVERTER APPLICATIONS
The LT3759 can be configured as a dual-inductor inverting
topology, as shown in Figure 9. The VOUT to VIN ratio is:
VOUT – VD
VIN =D
1−D
In continuous conduction mode (CCM).
APPLICATIONS INFORMATION
Figure 9. A Simplified Inverting Converter
RSENSE
CDC
VIN
CIN
L1
D1
COUT
VOUT
3759 F09
+
GATE
GND
LT3759
SENSE
L2
M1
+
–
+–
+
LT3 759
Vour VD
DMAX
1’DMAX
L7HEJWEGR 23
LT3759
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Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (VOUT) and the input voltage (VIN).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =VOUT – VD
VOUT – VD– VIN(MIN)
Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections
The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an inverting
converter are similar to those of the SEPIC converter. Please
refer to the corresponding SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost and SEPIC converters
for similar output ripples. This is due to the fact that, in
the inverting converter, the inductor L2 is in series with the
output, and the ripple current flowing through the output
capacitors are continuous. The output ripple voltage is
produced by the ripple current of L2 flowing through the
ESR and bulk capacitance of the output capacitor:
∆VOUT(P−P) = ∆IL2 •ESRCOUT +1
8•fOSC •COUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
IRMS(COUT) >0.3 •DIL2
Inverting Converter: Selecting the DC Coupling
Capacitor
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 9) should be larger than the maximum
input voltage minus the output voltage (negative voltage):
V
CDC
>V
IN(MAX)
– V
OUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
IRMS(CDC) >IO(MAX) •DMAX
1–DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
Board Layout
The high speed operation of the LT3759 demands careful
attention to board layout and component placement. The
exposed pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the exposed pad and the ground
plane of the board. For the LT3759 to deliver its full output
power, it is imperative that a good thermal path be pro-
vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher di/
dt. The following high di/dt loops of different topologies
should be kept as tight as possible to reduce inductive
ringing:
• In boost configuration, the high di/dt loop contains the
output capacitor, the sensing resistor, the power MOSFET
and the Schottky diode.
APPLICATIONS INFORMATION
LT3 759
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• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
power MOSFET and sensing resistor. The high di/dt
secondary loop contains the output capacitor, the sec-
ondary winding and the output diode.
• In SEPIC configuration, the high di/dt loop contains
the power MOSFET, sense resistor, output capacitor,
Schottky diode and the coupling capacitor.
• In inverting configuration, the high di/dt loop contains
power MOSFET, sense resistor, Schottky diode and the
coupling capacitor.
Check the stress on the power MOSFET by measuring its
drain-to-source voltage directly across the device terminals
(reference the ground of a single scope probe directly to
the source pad on the PC board). Beware of inductive
ringing, which can exceed the maximum specified voltage
rating of the MOSFET. If this ringing cannot be avoided,
and exceeds the maximum rating of the device, either
choose a higher voltage device or specify an avalancher-
ated power MOSFET.
The small-signal components should be placed away from
high frequency switching nodes. For optimum load regula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
the top of the output capacitor (Kelvin connection), staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3759 in order to keep the high impedance
FBX node short.
Figure 10 shows the suggested layout of 1.8V to 3.3V
input, 5V/2A Output Boost Converter.
APPLICATIONS INFORMATION
Figure 10. The Suggested Boost Converter Layout
3759 F10
VOUT
L1
VIAS TO GROUND
PLANE
D1
COUT1
COUT2
CIN
1
2
8
7
3
4
6
5
M1
RC
R1
R2
CSS
RT
R3
R4
CVCC
CDRIVE
CC1
CC2
LT3759
13
2
3
1
4
5
6
10
11
12
7
8
9
RS
RPGOOD
VIN
VIN
VIAS TO VIN
GND
LT3 759
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LT3759
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For more information www.linear.com/3759
TYPICAL APPLICATIONS
1.8V to 3.3V Input, 5V/2A Output Boost Converter
Efficiency vs Output Current Load Step Response at VIN = 2.5V
OUTPUT CURRENT (A)
0.001
EFFICIENCY (%)
60
80
100
1
3759 TA02b
40
0.01 0.1 10
10
20
30
50
70
90
0
VIN = 1.8V
VIN = 3.3V
VOUT
500mV/DIV
(AC)
IOUT
1A/DIV
3759 TA02c
500µs/DIV
1.6A
0.4A
SENSE
LT3759
VIN DRIVE
VIN
1.8V TO 3.3V CIN
47µF
6.3V
X5R
RT
27.4k
300kHz
GATE
PGOOD
FBX
GND INTVCC
EN/UVLO
SYNC
RT
SS
VC
L1
2.2µH
R3
59k
R4
124k
CSS
0.1µF
M1: VISHAY SiA414DJ
L1: TOKO FDA1055-2R2M
D1: VISHAY 6CWQ06FN
RC
7.5k
CC1
22nF
R1
15.8k
1%
R2
34k
1%
RS
5mΩ
0.5W
CC2
100pF
CVCC
4.7µF
10V
X5R
VOUT
5V
2A
COUT2
100µF
6.3V
X5R
×3
3759 TA02a
D1
M1
R5
10k
LT3 759
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TYPICAL APPLICATIONS
8V to 16V Input, 24V/2A Output Boost Converter
Efficiency vs Output Current Load Step Response at VIN = 12V
OUTPUT CURRENT (A)
0.001
EFFICIENCY (%)
60
80
100
1
3759 TA03b
40
0.01 0.1 10
10
20
30
50
70
90
0
VIN = 8V
VIN = 16V VOUT
500mV/DIV
(AC)
IOUT
1A/DIV
3759 TA03c
500µs/DIV
1.6A
0.4A
SENSE
LT3759
VIN DRIVE
VIN
8V TO 16V CIN
22µF
25V
X5R
RT
27.4k
300kHz
GATE
PGOOD
FBX
GND INTVCC
EN/UVLO
SYNC
RT
SS
VC
L1
10µH
R3
200k
R4
43.2k
CSS
0.1µF
RC
20k
CC1
10nF
R1
16.2k
1%
R2
226k
1%
RS
5mΩ
0.5W
CC2
100pF
CVCC
4.7µF
10V
X5R
VOUT
24V
2A
COUT2
22µF
25V
X5R
3759 TA03a
COUT1
33µF
35V
×2
D1
M1
R5
100k
+
M1: VISHAY SILICONIX Si4840 BDY
L1: WÜRTH ELEKTRONIK 7443321000
D1: VISHAY 6CWQ06FN
LT3 759
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LT3759
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3759fc
For more information www.linear.com/3759
TYPICAL APPLICATIONS
1.8V to 5V Input, 3.3V/3A Output SEPIC Converter
Efficiency vs Output Current Load Step Response at VIN = 2.5V
VOUT
500mV/DIV
(AC)
IOUT
1A/DIV
3759 TA04c
500µs/DIV
2.5A
0.5A
OUTPUT CURRENT (A)
0.001
EFFICIENCY (%)
60
80
100
1
3759 TA04b
40
0.01 0.1 10
10
20
30
50
70
90
0
VIN = 2.5V
SENSE
LT3759
VIN DRIVE
VIN
1.8V TO 5V
CIN
47µF
10V
27.4k
300kHz
CDC
4.7µF
10V, X5R, ×2
GATE
PGOOD
FBX
GND INTVCC
EN/UVLO
SYNC
RT
SS
VC
L1A
L1B
IL1A
VSW
IL1B
59k
124k
0.1µF 3.01k
22nF
15.8k
1%
16.9k
1%
0.004Ω
1W
4.7µF
10V
X5R
VOUT
3.3V
2A, 1.8V ≤ VIN ≤ 3V
3A, 3V < VIN ≤ 5V
COUT
100µF
6.3V
X5R
×3
3759 TA04a
D1
M1
10k
M1: VISHAY Si7858BDP
L1A, L1B: COILTRONICS DRQ127-4R7
D1: VISHAY 6CWQ06FN
LT3 759
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TYPICAL APPLICATIONS
2.5V to 36V Input, 12V/1A Output SEPIC Converter
(Automotive 12V Regulator)
Efficiency vs Output Current Load Step Response at VIN = 12V
Frequency Foldback Waveforms When Output Short-Circuits
SENSE
LT3759
VIN DRIVE
VIN
2.5V TO 36V CIN
4.7µF
50V
×4
41.2k
200kHz
CDC
4.7µF
50V, X5R, ×2
GATE
PGOOD
FBX
GND INTVCC
EN/UVLO
SYNC
RT
SS
VC
L1A
L1BIL1B
IL1A
105k
118k
0.1µF 7.5k
22nF
15.8k
1%
105k
1%
0.005Ω
0.5W
4.7µF
10V
X5R
VOUT
12V
0.5A, 2.5V ≤ VIN ≤ 8V
2A, 8V < VIN ≤ 36V
COUT2
10µF
25V
X5R
3759 TA05a
COUT1
47µF
20V
×4
D1
M1
100k
+
VSW
M1: VISHAY SILICONIX Si7460DP
L1A, L1B: COILTRONICS DRQ127-150
D1: VISHAY 6CWQ06FN
OUTPUT CURRENT (A)
0
EFFICIENCY (%)
90
95
100
1.5 2.5
3759 TA05b
85
0.5 1 2
80
75
VIN = 12V
VOUT
500mV/DIV
(AC)
IOUT
1A/DIV
3759 TA05c
500µs/DIV
1.6A
0.4A
VOUT
10V/DIV
VSW
20V/DIV
IL1A + L1B
5A/DIV
3759 TA05d
20µs/DIV
LT3 759
HI—
Hit—1
TN
WE
M V
, ‘
W
WWWWHWWWW
MWMWWWWVWW
L7HEJWEGR 29
LT3759
29
3759fc
For more information www.linear.com/3759
TYPICAL APPLICATIONS
5V to 15V Input, –5V/3A Output Inverting Converter
Efficiency vs Output Current Load Step Response at VIN = 10V
Frequency Foldback Waveforms When Output Short-Circuits
OUTPUT CURRENT (A)
0.001
EFFICIENCY (%)
60
80
100
1
3759 TA06b
40
0.01 0.1 10
10
20
30
50
70
90
0
VIN = 15V
VIN = 5V
VOUT
500mV/DIV
(AC)
IOUT
2A/DIV
3759 TA06c
500µs/DIV
4A
0.5A
VOUT
5V/DIV
VSW
10V/DIV
IL1A + L1B
5A/DIV
3759 TA06d
20µs/DIV
SENSE
LT3759
VIN DRIVE
VIN
5V TO 15V CIN
47µF
16V
X5R
27.4k
300kHz
GATE
PGOOD
FBX
GND INTVCC
EN/UVLO
SYNC
RT
SS
VC
R2
105k
R1
45.3k
0.1µF
9.1k
10nF
15.8k
84.5k
CDC
4.7µF
25V, X5R, ×2
5mΩ
0.5W
CVCC
4.7µF
10V
X5R
VOUT
–5V
3A, 5V ≤ VIN ≤ 10V
4A, 10V < VIN ≤ 15V
COUT
47µF
6.3V, X5R
×4
3759 TA06a
M1
100k L1B
3.3µH
L1A
3.3µH
D1
M1: VISHAY SILICONIX Si7848BDP
L1A, L1B: COILTRONICS DRQ127-3R3
D1: VISHAY 6CWQ03FN
LT3 759
3O L7ELUEN2
LT3759
30
3759fc
For more information www.linear.com/3759
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
MSOP (MSE12) 0911 REV F
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.22 –0.38
(.009 – .015)
TYP
0.86
(.034)
REF
0.650
(.0256)
BSC
12
12 11 10 9 8 7
7
DETAIL “B”
16
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL
NOT EXCEED 0.254mm (.010") PER SIDE.
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
RECOMMENDED SOLDER PAD LAYOUT
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.845 ±0.102
(.112 ±.004)
2.845 ±0.102
(.112 ±.004)
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
1.651 ±0.102
(.065 ±.004)
1.651 ±0.102
(.065 ±.004)
0.1016 ±0.0508
(.004 ±.002)
1 2 3 4 5 6
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.406 ±0.076
(.016 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
DETAIL “B”
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
0.12 REF
0.35
REF
5.23
(.206)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
0.42 ±0.038
(.0165 ±.0015)
TYP
0.65
(.0256)
BSC
MSE Package
12-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1666 Rev F)
LT3 759
L7 LJUW 3 1
LT3759
31
3759fc
For more information www.linear.com/3759
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A12/11 SS Pull-Up Current MIN and TYP values updated and INTVCC Current in Shutdown TYP value updated in Electrical
Characteristics table. 3, 4
Revised Typical Application drawing TA02a 25
B4/12 Revised Typical Applications Schematic TA01a
Added UN/UVLO Rising Spec
1
4
C1/13 Corrected M1 part number on Typical Application 25
LT3 759
L7LJCUEN2
32
LT3759
32
3759fc
For more information www.linear.com/3759
LINEAR TECHNOLOGY CORPORATION 2011
LT 0113 REV C • PRINTED IN USA
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/3759
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT3757 Boost, Flyback, SEPIC and Inverting
Controller 2.9V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation
Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages
LT3758 Boost, Flyback, SEPIC and Inverting
Controller 5.5V ≤ VIN ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable Operation
Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages
LT3957 Boost, Flyback, SEPIC and Inverting
Converter with 5A, 40V Switch 3V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable Operation
Frequency, 5mm × 6mm QFN Package
LT3958 Boost, Flyback, SEPIC and Inverting
Converter with 3.3A, 84V Switch 5V ≤ VIN ≤ 80V, Current Mode Control, 100kHz to 1MHz Programmable Operation
Frequency, 5mm × 6mm QFN Package
LTC3872 No RSENSE Boost Controller 2.75V ≤ VIN ≤ 9.8V, TSOT-23 and 2mm × 3mm DFN-8
1.8V to 5V Input, –5V/2A Output Inverting Converter
Efficiency vs Output Current
SENSE
DRIVE
LT3759
VIN
VIN
1.8V TO 5V CIN
47µF
10V
X5R
27.4k
300kHz
CDC
4.7µF ×2
25V, X5R
1µF
16V
X5R
GATE
FBX
GND INTVCC
EN/UVLO
SYNC
PGOOD
RT
SS
VC
L1B
3.3µH
L1A, 3.3µH
1:1
59k
124k
0.1µF 9.1k
10nF
5mΩ
0.5W
100k
TIE TO GND
IF NOT USED
CVCC
4.7µF
10V
X5R
VOUT
–5V
1A, 1.8V ≤ VIN ≤ 2.5V
2A, 2.5V < VIN ≤ 5V
COUT
100µF
6.3V, X5R
×2
3759 TA07a
D2
M1
D1
M1: VISHAY SILICONIX Si74116DY
L1A, L1B: COILTRONICS DRQ127-3R3
D1: VISHAY 6CWQ03FN
D2: PHILIPS PMEG2005EJ
84.5k
15.8k
OUTPUT CURRENT (A)
0
EFFICIENCY (%)
95
100
1.5
3759 TA07b
0.5 1 2.52
75
80
85
90
70
VIN = 5V
VIN = 2.5V
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