SN74VMEH22501GQLR Datasheet by Texas Instruments

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SN74VMEH22501
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8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
Check for Samples: SN74VMEH22501
1FEATURES
Member of the Texas Instruments Widebus™ ESD Protection Exceeds JESD 22
Family 2000-V Human-Body Model (A114-A)
UBT™ Transceiver Combines D-Type Latches 200-V Machine Model (A115-A)
and D-Type Flip-Flops for Operation in 1000-V Charged-Device Model (C101)
Transparent, Latched, or Clocked Modes
DGG OR DGV PACKAGE
OEC™ Circuitry Improves Signal Integrity and (TOP VIEW)
Reduces Electromagnetic Interference (EMI)
Compliant With VME64, 2eVME, and 2eSST
Protocol
Bus Transceiver Split LVTTL Port Provides a
Feedback Path for Control and Diagnostics
Monitoring
I/O Interfaces Are 5-V Tolerant
B-Port Outputs (–48 mA/64 mA)
Y and A-Port Outputs (–12 mA/12 mA)
• Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
Bus Hold on 3A-Port Data Inputs
• 26-Equivalent Series Resistor on 3A Ports
and Y Outputs
Flow-Through Architecture Facilitates Printed
Circuit Board Layout
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESCRIPTION/ORDERING INFORMATION
The SN74VMEH22501 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is
designed for 3.3-V VCC operation with 5-V tolerant inputs. The UBT™ transceiver allows transparent, latched, and
flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a
feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards
operating at LVTTL logic levels and VME64, VME64x, or VME320(1) backplane topologies.
(1) VME320 is a patented backplane construction by Arizona Digital, Inc.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2001–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
High-speed backplane operation is a direct result of the improved OEC™ circuitry and high drive that has been
designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive
loads and include pseudo-ETL input thresholds (½ VCC ± 50 mV) for increased noise immunity. These
specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols in VITA 1.5. With
proper design of a 21-slot VME system, a designer can achieve 320-Mbyte transfer rates on linear backplanes
and, possibly, 1-Gbyte transfer rates on the VME320 backplane.
All inputs and outputs are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs.
Active bus-hold circuitry holds unused or undriven 3A-port inputs at a valid logic state. Bus-hold circuitry is not
provided on 1A or 2A inputs, any B-port input, or any control input. Use of pullup or pulldown resistors with the
bus-hold circuitry is not recommended.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry prevents damaging current to backflow through the device when it is powered off/on. The power-up
3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents
driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections,
preventing disturbance of active data on the backplane during card insertion or removal, and permits true
live-insertion capability.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, output-enable (OE and OEBY) inputs should be tied
to VCC through a pullup resistor and output-enable (OEAB) inputs should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by the drive capability of the device connected to this
input.
ORDERING INFORMATION
TAPACKAGE(1) ORDERABLE PART NUMBER TOP-SIDE MARKING
BGA MicroStar™ Tape and reel SN74VMEH22501ZQLR VK501
Junior – ZQL
TSSOP – DGG Tape and reel SN74VMEH22501DGGR VMEH22501
0°C to 85°C
TVSOP – DGV Tape and reel SN74VMEH22501DGVR VK501
VFBGA – GQL Tape and reel SN74VMEH22501GQLR VK501
(1) Package drawings, thermal data, and symbolization are available at www.ti.com/sc/packaging.
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‘5‘ TEXAS INSTRUMENTS Izaass 0000000000 0000000000 0000 0000 0000 0000 0000000000 0000000000 ABCDEFGHJK
SN74VMEH22501
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GQL OR ZQL PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS(1)
123456
A1OEBY NC NC NC NC 1OEAB
B1Y 1A GND GND VCC 1B
C2Y 2A VCC VCC BIAS VCC 2B
D3A1 2OEBY GND GND 2OEAB 3B1
E3A2 LE VCC 3B2
F3A3 OE VCC 3B3
G3A4 CLKBA GND GND CLKAB 3B4
H3A5 3A6 VCC VCC 3B6 3B5
J3A7 3A8 GND GND 3B8 3B7
KDIR NC NC NC NC VCC
(1) NC - No internal connection
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FUNCTIONAL DESCRIPTION
The SN74VMEH22501 is a high-drive (–48/64 mA), 8-bit UBT transceiver containing D-type latches and D-type
flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true logic. The
device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus transceivers.
Functional Description for Two 1-Bit Bus Transceivers
The OEAB inputs control the activity of the 1B or 2B port. When OEAB is high, the B-port outputs are active.
When OEAB is low, the B-port outputs are disabled.
Separate 1A and 2A inputs and 1Y and 2Y outputs provide a feedback path for control and diagnostics
monitoring. The OEBY inputs control the 1Y or 2Y outputs. When OEBY is low, the Y outputs are active. When
OEBY is high, the Y outputs are disabled.
The OEBY and OEAB inputs can be tied together to form a simple direction control where an input high yields
A data to B bus and an input low yields B data to Y bus.
1-BIT BUS TRANSCEIVER FUNCTION TABLE
INPUTS OUTPUT MODE
OEAB OEBY
L H Z Isolation
H H A data to B bus True driver
L L B data to Y bus
H L A data to B bus, B data to Y bus True driver with feedback path
Functional Description for 8-Bit UBT Transceiver
The 3A and 3B data flow in each direction is controlled by the OE and direction-control (DIR) inputs. When OE is
low, all 3A- or 3B-port outputs are active. When OE is high, all 3A- or 3B-port outputs are in the high-impedance
state.
FUNCTION TABLE
INPUTS OUTPUT
OE DIR
H X Z
L H 3A data to 3B bus
L L 3B data to 3A bus
The UBT transceiver functions are controlled by latch-enable (LE) and clock (CLKAB and CLKBA) inputs. For
3A-to-3B data flow, the UBT operates in the transparent mode when LE is high. When LE is low, the 3A data is
latched if CLKAB is held at a high or low logic level. If LE is low, the 3A data is stored in the latch/flip-flop on the
low-to-high transition of CLKAB.
The UBT transceiver data flow for 3B to 3A is similar to that of 3A to 3B, but uses CLKBA.
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Table 1. UBT TRANSCEIVER FUNCTION TABLE(1)
INPUTS OUTPUT MODE
3B
OE LE CLKAB 3A
H X X X Z Isolation
L L H X B0(2) Latched storage of 3A data
L L L X B0(3)
L H X L L True transparent
L H X H H
L L L L Clocked storage of 3A data
L L H H
(1) 3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA.
(2) Output level before the indicated steady-state input conditions were established, provided that CLKAB
was high before LE went low
(3) Output level before the indicated steady-state input conditions were established
The UBT transceiver can replace any of the functions shown in Table 2.
Table 2. SN74VMEH22501 UBT Transceiver
Replacement Functions
FUNCTION 8 BIT
Transceiver '245, '623, '645
Buffer/driver '241, '244, '541
Latched transceiver '543
Latch '373, '573
Registered transceiver '646, '652
Flip-flop '374, '574
SN74VMEH22501 UBT transceiver replaces all above functions
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l TEXAS INSTRUMENTS 1OEAB _7 DIR CLKAB LE CLKBA KAI 351 \—V—/ Tn Seven Other Channels
1D
C1
CLK
1D
C1
CLK
3B1
CLKAB
LE
CLKBA
3A1
To Seven Other Channels
OE
DIR
1OEAB
1OEBY
1A
1Y
2OEAB
2OEBY
2A
2Y
2B
1B
48
1
2
3
41
8
5
6
14
24
32
11
17
9
46
43
40
Pin numbers shown are for the DGG and DGV packages.
SN74VMEH22501
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LOGIC DIAGRAM (POSITIVE LOGIC)
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Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC,Supply voltage range –0.5 4.6 V
BIAS VCC
VIInput voltage range(2) –0.5 7 V
VOVoltage range applied to any output in the high-impedance or power-off state(2) –0.5 7 V
3A port or Y output –0.5 VCC + 0.5
Voltage range applied to any output in the high or low
VOV
state(2) B port –0.5 4.6
3A port or Y output 50
IOOutput current in the low state mA
B port 100
3A port or Y output –50
IOOutput current in the high state mA
B port –100
IIK Input clamp current VI< 0 –50 mA
IOK Output clamp current VO< 0 or VO> VCC, B port –50 mA
DGG package 70
qJA Package thermal impedance(3) DGV package 58 °C/W
GQL/ZQL package 42
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1) (2)
MIN NOM MAX UNIT
VCC,Supply voltage 3.15 3.3 3.45 V
BIAS VCC
Control inputs or A port VCC 5.5
VIInput voltage V
B port VCC 5.5
Control inputs or A port 2
VIH High-level input voltage V
B port 0.5 VCC + 50 mV
Control inputs or A port 0.8
VIL Low-level input voltage V
B port 0.5 VCC – 50 mV
IIK Input clamp current –18 mA
3A port and Y output –12
IOH High-level output current mA
B port –48
3A port and Y output 12
IOL Low-level output current mA
B port 64
Δt/Δv Input transition rise or fall rate Outputs enabled 10 ns/V
Δt/ΔVCC Power-up ramp rate 20 ms/V
TAOperating free-air temperature 0 85 °C
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control inputs can be connected at any
time, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is acceptable, but
generally, GND is connected first.
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Electrical Characteristics
over recommended operating free-air temperature range for A and B ports (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK VCC = 3.15 V, II= –18 mA –1.2 V
3A port, any B ports, VCC = 3.15 V to 3.45 V, IOH = –100 mA VCC – 0.2
and Y outputs
IOH = –6 mA 2.4
3A port and Y outputs VCC = 3.15 V
VOH V
IOH = –12 mA 2
IOH = –24 mA 2.4
Any B port VCC = 3.15 V IOH = –48 mA 2
3A port, any B ports, VCC = 3.15 V to 3.45 V, IOL = 100 mA 0.2
and Y outputs
IOL = 6 mA 0.55
3A port and Y outputs VCC = 3.15 V IOL = 12 mA 0.8
VOL V
IOL = 24 mA 0.4
Any B port VCC = 3.15 V IOL = 48 mA 0.55
IOL = 64 mA 0.6
VCC = 3.45 V, VI= VCC or GND ±1
Control inputs,
IImA
1A and 2A VCC = 0 or 3.45 V, VI= 5.5 V 5
3A port, any B port,
IOZH (2) VCC = 3.45 V, VO= VCC or 5.5 V 5 mA
and Y outputs
3A port and Y outputs –5
IOZL (2) VCC = 3.45 V, VO= GND mA
Any B port –20
Ioff VCC = 0, BIAS VCC = 0, VIor VO= 0 to 5.5 V ±10 mA
IBHL (3) 3A port VCC = 3.15 V, VI= 0.8 V 75 mA
IBHH (4) 3A port VCC = 3.15 V, VI= 2 V –75 mA
IBHLO (5) 3A port VCC = 3.45 V, VI= 0 to VCC 500 mA
IBHHO (6) 3A port VCC = 3.45 V, VI= 0 to VCC –500 mA
VCC 1.5 V, VO= 0.5 V to VCC,
IOZ(PU/PD) (7) ±10 mA
VI= GND or VCC, OE = don't care
Outputs high 30
VCC = 3.45 V, IO= 0,
ICC Outputs low 30 mA
VI= VCC or GND Outputs disabled 30
VCC = 3.45 V, IO= 0, Outputs enabled 76 mA/
VI= VCC or GND, clock
ICCD One data input switching at MHz/
Outputs disabled 19
one-half clock frequency, input
50% duty cycle
VCC = 3.15 V to 3.45 V, One input at VCC – 0.6 V,
ΔICC (8) 750 mA
Other inputs at VCC or GND
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
(2) For I/O ports, the parameters IOZH and IOZL include the input leakage current.
(3) The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to
GND, then raising it to VIL max.
(4) The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC, then lowering it to VIH min.
(5) An external driver must source at least IBHLO to switch this node from low to high.
(6) An external driver must sink at least IBHHO to switch this node from high to low.
(7) High-impedance state during power up or power down
(8) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range for A and B ports (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
1A and 2A inputs 2.8
CiVI= 3.15 V or 0 pF
Control inputs 2.6
Co1Y or 2Y outputs VO= 3.15 V or 0 5.6 pF
3A port 7.9
Cio VCC = 3.3 V, VO= 3.3 V or 0 pF
Any B port 11 12.5
Live-Insertion Specifications
over recommended operating free-air temperature range for B port
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VCC = 0 to 3.15 V, BIAS VCC = 3.15 V to 3.45 V, IO(DC) = 0 5 mA
ICC (BIAS VCC)VCC = 3.15 V to 3.45 V(2), BIAS VCC = 3.15 V to 3.45 V, IO(DC) = 0 10 mA
VOVCC = 0, BIAS VCC = 3.15 V to 3.45 V 1.3 1.5 1.7 V
VO= 0, BIAS VCC = 3.15 V –20 –100
IOVCC = 0 mA
VO= 3 V, BIAS VCC = 3.15 V 20 100
(1) All typical values are at VCC = 3.3 V, TA= 25°C.
(2) VCC – 0.5 V < BIAS VCC
Timing Requirements for UBT Transceiver
over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2)
MIN MAX UNIT
fclock Clock frequency 120 MHz
LE high 2.5
twPulse duration ns
CLK high or low 3
Data high 2.1
3A before CLKData low 2.2
CLK high 2
3A before LECLK low 2
tsu Setup time ns
Data high 2.5
3B before CLKData low 2.7
CLK high 2
3B before LECLK low 2
Data high 0
3A after CLKData low 0
CLK high 1
3A after LECLK low 1
thHold time ns
Data high 0
3B after CLKData low 0
CLK high 1
3B after LECLK low 1
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Switching Characteristics for Bus Transceiver Function
over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2)
FROM TO
PARAMETER MIN TYP MAX UNIT
(INPUT) (OUTPUT)
tPLH 5.1 8.9
1A or 2A 1B or 2B ns
tPHL 4.5 7.8
tPLH 7.2 14.5
1A or 2A 1Y or 2Y ns
tPHL 6.1 13
tPZH 4.6 8.1
OEAB 1B or 2B ns
tPZL 3.7 7.4
tPHZ 3.3 9.7
OEAB 1B or 2B ns
tPLZ 1.8 4.8
trTransition time, B port (10%–90%) 4.3 ns
tfTransition time, B port (90%–10%) 4.3 ns
tPLH 1.6 5.6
1B or 2B 1Y or 2Y ns
tPHL 1.6 5.6
tPZH 1.2 5.6
OEBY 1Y or 2Y ns
tPZL 1.8 4.9
tPHZ 1.4 5.4
OEBY 1Y or 2Y ns
tPLZ 1.7 4.5
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Switching Characteristics for UBT Transceiver
over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2)
FROM TO
PARAMETER MIN TYP MAX UNIT
(INPUT) (OUTPUT)
fmax 120 MHz
tPLH 5.5 9.3
3A 3B ns
tPHL 4.7 8.3
tPLH 6 10.6
LE 3B ns
tPHL 4.9 8.7
tPLH 5.8 10.1
CLKAB 3B ns
tPHL 4.6 8.4
tPZH 4.6 9.3
OE 3B ns
tPZL 3.5 8.5
tPHZ 4.8 9.3
OE 3B ns
tPLZ 2.4 5.7
trTransition time, B port (10%–90%) 4.3 ns
tfTransition time, B port (90%–10%) 4.3 ns
tPLH 1.7 5.9
3B 3A ns
tPHL 1.7 5.9
tPLH 1.7 5.9
LE 3A ns
tPHL 1.7 5.9
tPLH 1.4 5.5
CLKBA 3A ns
tPHL 1.4 5.5
tPZH 1.5 6.2
OE 3A ns
tPZL 2.1 5.5
tPHZ 1.8 6.2
OE 3A ns
tPLZ 2.3 5.6
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Skew Characteristics for Bus Transceiver
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 1 and Figure 2)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
tsk(LH) 0.8
1A or 2A 1B or 2B ns
tsk(HL) 0.7
tsk(LH) 0.7
1B or 2B 1Y or 2Y ns
tsk(HL) 0.6
1A or 2A 1B or 2B 1.7
tsk(t) (1) ns
1B or 2B 1Y or 2Y 1.2
1A or 2A 1B or 2B 2.8
tsk(pp) ns
1B or 2B 1Y or 2Y 1.4
(1) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
Skew Characteristics for UBT
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 1 and Figure 2)
FROM TO
PARAMETER MIN MAX UNIT
(INPUT) (OUTPUT)
tsk(LH) 1.3
3A 3B ns
tsk(HL) 1.1
tsk(LH) 0.8
CLKAB 3B ns
tsk(HL) 0.8
tsk(LH) 0.7
3B 3A ns
tsk(HL) 0.6
tsk(LH) 0.7
CLKBA 3A ns
tsk(HL) 0.6
3A 3B 1.9
CLKAB 3B 2.1
tsk(t) (1) ns
3B 3A 1.2
CLKBA 3A 1
3A 3B 2.8
CLKAB 3B 2.7
tsk(pp) ns
3B 3A 1.3
CLKBA 3A 1.2
(1) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
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l TEXAS INSTRUMENTS me Oulpul Under Test cL : so pF (see Nole A) LOAD CIRCUIT
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500
500
tPLH tPHL
Output Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH - 0.3 V
0 V
3 V
0 V
0 V
tw
Input
3 V 3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Timing
Input
Data
Input
Output
Input
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
B-to-A Skew
Open
6 V
GND
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
6 V
1.5 V 0 V
3 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
VCC/2 VCC/2
VCC/2 VCC/2
SN74VMEH22501
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SCES357F JULY 2001REVISED FEBRUARY 2010
PARAMETER MEASUREMENT INFORMATION
A PORT
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 2001–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): SN74VMEH22501
l TEXAS INSTRUMENTS me Oulpul Under Test cL : so pF (see Nole A) LOAD CIRCUIT H74»
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500
500
tPLH tPHL
Output Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH - 0.3 V
0 V
3 V
0 V
0 V
tw
Input
3 V 3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Timing
Input
Data
Input
Output
Input
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
A-to-B Skew
Open
6 V
GND
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2 ns, tf 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
6 V
0 V
3 V
VCC/2
VCC/2
VCC/2
VCC/2
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
SN74VMEH22501
SCES357F JULY 2001REVISED FEBRUARY 2010
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PARAMETER MEASUREMENT INFORMATION
B PORT
Figure 2. Load Circuit and Voltage Waveforms
14 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74VMEH22501
l TEXAS INSTRUMENTS 0.42" 0.42" 0.84" 0.34” 0.42" Slol I Slot 2 Slol 3 Slol19 Slot 20 Slot T Un‘oaded backp‘ane trace natural \mpedence {20) \s 45 0.45 0 to so 0 IS anowed w‘m so I) being Idea‘. 2 Card stub natured \mpedence (20} \s 60 0,
5 V
0.42” 0.84”
1.5” 1.5” 1.5”1.5”
0.84” 0.42”
Rcvr Rcvr Rcvr
Slot 2 Slot 3 Slot 19 Slot 20
Conn. Conn. Conn. Conn.
1.5”
Rcvr
Slot 1
Conn.
0.42”
Drvr
1.5
Slot 21
Conn.
0.42”
330
470
ZO
5 V
330
470
ZO
Unloaded backplane trace natural impedence (ZO) is 45 Ω. 45 to 60 is allowed, with 50 being ideal.
Card stub natural impedence (ZO) is 60 .
Rcvr
SN74VMEH22501
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SCES357F JULY 2001REVISED FEBRUARY 2010
Distributed-Load Backplane Switching Characteristics
The preceding switching characteristics tables show the switching characteristics of the device into the lumped
load shown in the parameter measurement information (PMI) (see Figure 1 and Figure 2). All logic devices
currently are tested into this type of load. However, the designer's backplane application probably is a distributed
load. For this reason, this device has been designed for optimum performance in the VME64x backplane as
shown in Figure 3.
Figure 3. VME64x Backplane
The following switching characteristics tables derived from TI-SPICE models show the switching characteristics
of the device into the backplane under full and minimum loading conditions, to help the designer better
understand the performance of the VME device in this typical backplane. See www.ti.com/sc/etl for more
information.
Driver in Slot 11, With Receiver Cards in All Other Slots (Full Load)
Switching Characteristics for Bus Transceiver Function
over recommended operating conditions (unless otherwise noted) (see Figure 3)
FROM TO
PARAMETER MIN TYP(1) MAX UNIT
(INPUT) (OUTPUT)
tPLH 5.9 8.5
1A or 2A 1B or 2B ns
tPHL 5.5 8.7
tr(2) Transition time, B port (10%–90%) 9 8.6 11.4 ns
tf(2) Transition time, B port (90%–10%) 8.9 9 10.8 ns
(1) All typical values are at VCC = 3.3 V, TA= 25°C. All values are derived from TI-SPICE models.
(2) All trand tftimes are taken at the first receiver.
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Switching Characteristics for UBT
over recommended operating conditions (unless otherwise noted) (see Figure 3)
FROM TO
PARAMETER MIN TYP(1) MAX UNIT
(INPUT) (OUTPUT)
tPLH 6.2 8.9
3A 3B ns
tPHL 5.6 9
tPLH 6.1 9.1
LE 3B ns
tPHL 5.6 9
tPLH 6.2 9.1
CLKAB 3B ns
tPHL 5.7 9
tr(2) Transition time, B port (10%–90%) 9 8.6 11.4 ns
tf(2) Transition time, B port (90%–10%) 8.9 9 10.8 ns
(1) All typical values are at VCC = 3.3 V, TA= 25°C. All values are derived from TI-SPICE models.
(2) All trand tftimes are taken at the first receiver.
Skew Characteristics for Bus Transceiver
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 3)
FROM TO
PARAMETER MIN TYP(1) MAX UNIT
(INPUT) (OUTPUT)
tsk(LH) 2.5
1A or 2A 1B or 2B ns
tsk(HL) 3
tsk(t) (2) 1A or 2A 1B or 2B 1 ns
tsk(pp) 1A or 2A 1B or 2B 0.5 3.4 ns
(1) All typical values are at VCC = 3.3 V, TA= 25°C. All values are derived from TI-SPICE models.
(2) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
Skew Characteristics for UBT
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 3)
FROM TO
PARAMETER MIN TYP(1) MAX UNIT
(INPUT) (OUTPUT)
tsk(LH) 2.4
3A 3B ns
tsk(HL) 3.4
tsk(LH) 2.7
CLKAB 3B ns
tsk(HL) 3.4
3A 3B 1
tsk(t) (2) ns
CLKAB 3B 1
3A 3B 0.5 3.4
tsk(pp) ns
CLKAB 3B 0.6 3.5
(1) All typical values are at VCC = 3.3 V, TA= 25°C. All values are derived from TI-SPICE models.
(2) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
Driver in Slot 1, With One Receiver in Slot 21 (Minimum Load)
Switching Characteristics for Bus Transceiver Function
over recommended operating conditions (unless otherwise noted) (see Figure 3)
16 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74VMEH22501
l TEXAS INSTRUMENTS
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SCES357F JULY 2001REVISED FEBRUARY 2010
Switching Characteristics for Bus Transceiver Function (continued)
over recommended operating conditions (unless otherwise noted) (see Figure 3)
FROM TO
PARAMETER MIN TYP(1) MAX UNIT
(INPUT) (OUTPUT)
tPLH 5.5 7.4
1A or 2A 1B or 2B ns
tPHL 5.3 7.4
tr(2) Transition time, B port (10%–90%) 3.9 3.4 4.4 ns
tf(2) Transition time, B port (90%–10%) 3.7 3.4 4.8 ns
(1) All typical values are at VCC = 3.3 V, TA= 25°C. All values are derived from TI-SPICE models.
(2) All trand tftimes are taken at the first receiver.
Switching Characteristics for UBT
over recommended operating conditions (unless otherwise noted) (see Figure 3)
FROM TO
PARAMETER MIN TYP(1) MAX UNIT
(INPUT) (OUTPUT)
tPLH 5.8 7.9
3A 3B ns
tPHL 5.5 7.7
tPLH 5.9 8
LE 3B ns
tPHL 5.5 7.8
tPLH 5.9 8.1
CLKAB 3B ns
tPHL 5.5 7.7
tr(2) Transition time, B port (10%–90%) 3.9 3.4 4.4 ns
tf(2) Transition time, B port (90%–10%) 3.7 3.4 4.8 ns
(1) All typical values are at VCC = 3.3 V, TA= 25°C. All values are derived from TI-SPICE models.
(2) All trand tftimes are taken at the first receiver.
Skew Characteristics for Bus Transceiver
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 3)
FROM TO
PARAMETER MIN TYP(1) MAX UNIT
(INPUT) (OUTPUT)
tsk(LH) 1.7
1A or 2A 1B or 2B ns
tsk(HL) 2.1
tsk(t) (2) 1A or 2A 1B or 2B 1 ns
tsk(pp) 1A or 2A 1B or 2B 0.2 2.1 ns
(1) All typical values are at VCC = 3.3 V, TA= 25°C. All values are derived from TI-SPICE models.
(2) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
Copyright © 2001–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): SN74VMEH22501
l TEXAS INSTRUMENTS 165!) From Oulpul Under Test 235 Q 390 pF LOAD
From Output
Under Test
LOAD CIRCUIT
235
165
390 pF
5 V
SN74VMEH22501
SCES357F JULY 2001REVISED FEBRUARY 2010
www.ti.com
Skew Characteristics for UBT
for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air
temperature (see Figure 3)
FROM TO
PARAMETER MIN TYP(1) MAX UNIT
(INPUT) (OUTPUT)
tsk(LH) 2
3A 3B ns
tsk(HL) 2.3
tsk(LH) 2.1
CLKAB 3B ns
tsk(HL) 2.4
3A 3B 1
tsk(t) (2) ns
CLKAB 3B 1
3A 3B 0.2 2.5
tsk(pp) ns
CLKAB 3B 0.2 2.9
(1) All typical values are at VCC = 3.3 V, TA= 25°C. All values are derived from TI-SPICE models.
(2) tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs of
the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any outputs switching
in opposite directions, both low to high (LH) and high to low (HL) [tsk(t)].
By simulating the performance of the device using the VME64x backplane (see Figure 3), the maximum peak
current in or out of the B-port output, as the devices switch from one logic state to another, was found to be
equivalent to driving the lumped load shown in Figure 4.
Figure 4. Equivalent AC Peak Output-Current Lumped Load
In general, the rise- and fall-time distribution is shown in Figure 5. Since VME devices were designed for use into
distributed loads like the VME64x backplane (B/P), there are significant differences between low-to-high (LH) and
high-to-low (HL) values in the lumped load shown in the PMI (see Figure 1 and Figure 2).
18 Submit Documentation Feedback Copyright © 2001–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74VMEH22501
l TEXAS INSTRUMENTS ID :- :: Vcc
5.0
5.2
5.4
5.6
5.8
6.0
6.2
6.4
HL
LH
Full B/P Load Minimum B/P Load PMI Lumped Load
Time - ns
3.15 3.30 3.45
Peak IO(LH) - mA
VCC - V
137
136
135
134
133
132
131
130
129
128
3.15 3.30 3.45
Peak IO(HL) - mA
VCC - V
162
160
158
156
154
152
150
148
146
144
SN74VMEH22501
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SCES357F JULY 2001REVISED FEBRUARY 2010
Figure 5.
Characterization-laboratory data in Figure 6 and Figure 7 show the absolute ac peak output current, with different
supply voltages, as the devices change output logic state. A typical nominal process is shown to demonstrate the
devices' peak ac output drive capability.
Figure 6. Figure 7.
Copyright © 2001–2010, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): SN74VMEH22501
l TEXAS INSTRUMENTS : a. / / k / . / ’ / / r \ / / /. /
f - Switching Frequency - MHz
5
10
15
20
25
30
35
20 40 60 80 100 120
ICC(Enabled) - mA
VCC = 3.15 V
VCC = 3.3 V
VCC = 3.45 V
SUPPLY CURRENT
vs
FREQUENCY
A TO B
SN74VMEH22501
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www.ti.com
TYPICAL CHARACTERISTICS
Figure 8. Figure 9.
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Product Folder Link(s): SN74VMEH22501
l TEXAS INSTRUMENTS
VOH - High-Level Output Voltage - V
0 10 20 30 40 50 60 70 80 90 100
VCC = 3.15 V
VCC = 3.45 V
VCC = 3.3 V
IOH - High-Level Output Current - mA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
300
250
200
150
100
50
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VCC = 3.15 V
-20 -40 -60 -80 -90 -100-10 -30 -50 -700
VCC = 3.45 V
IOL - Low-Level Output Current - mA
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
OL
V- Low-Level Output Voltage - V
VCC = 3.3 V
SN74VMEH22501
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SCES357F JULY 2001REVISED FEBRUARY 2010
TYPICAL CHARACTERISTICS
Figure 10. VOL vs IOL
<br/>
Figure 11. VOH vs IOH
Copyright © 2001–2010, Texas Instruments Incorporated Submit Documentation Feedback 21
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VMEbus Summary
In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications.
The data-transfer protocols used to define the VMEbus came from the Motorola™ VERSA bus architecture that
owed its heritage to the then recently introduced Motorola 68000 microprocessor. The VMEbus, when
introduced, defined two basic data-transfer operations: single-cycle transfers consisting of an address and a data
transfer, and a block transfer (BLT) consisting of an address and a sequence of data transfers. These transfers
were asynchronous, using a master-slave handshake. The master puts address and data on the bus and waits
for an acknowledgment. The selected slave either reads or writes data to or from the bus, then provides a
data-acknowledge (DTACK*) signal. The VMEbus system data throughput was 40 Mbyte/s. Previous to the
VMEbus, it was not uncommon for the backplane buses to require elaborate calculations to determine loading
and drive current for interface design. This approach made designs difficult and caused compatibility problems
among manufacturers. To make interface design easier and to ensure compatibility, the developers of the
VMEbus architecture defined specific delays based on a 21-slot terminated backplane and mandated the use of
certain high-current TTL drivers, receivers, and transceivers.
In 1989, multiplexing block transfer (MBLT) effectively increased the number of bits from 32 to 64, thereby
doubling the transfer rate. In 1995, the number of handshake edges was reduced from four to two in the
double-edge transfer (2eVME) protocol, doubling the data rate again. In 1997, the VMEbus International Trade
Association (VITA) established a task group to specify a synchronous protocol to increase data-transfer rates to
320 Mbyte/s, or more. The unreleased specification, VITA 1.5 [double-edge source synchronous transfer
(2eSST)], is based on the asynchronous 2eVME protocol. It does not wait for acknowledgement of the data by
the receiver and requires incident-wave switching. Sustained data rates of 1 Gbyte/s, more than ten times faster
than traditional VME64 backplanes, are possible by taking advantage of 2eSST and the 21-slot VME320
star-configuration backplane. The VME320 backplane approximates a lumped load, allowing substantially
higher-frequency operation over the VME64x distributed-load backplane. Traditional VME64 backplanes with no
changes theoretically can sustain 320 Mbyte/s.
From BLT to 2eSST – A Look at the Evolution of VMEbus Protocols by John Rynearson, Technical Director,
VITA, provides additional information on VMEbus and can be obtained at www.vita.com.
Maximum Data Transfer Rates
FREQUENCY (MHz)
DATA BITS DATA TRANSFERS PER SYSTEM
DATE TOPOLOGY PROTOCOL PER CYCLE PER CLOCK CYCLE (Mbyte/s) BACKPLANE CLOCK
1981 VMEbus IEEE-1014 BLT 32 1 40 10 10
1989 VME64 MBLT 64 1 80 10 10
1995 VME64x 2eVME 64 2 160 10 20
1997 VME64x 2eSST 64 2-No Ack 160–320 10–20 20–40
1999 VME320 2eSST 64 2-No Ack 320–1000 2062.5 40–125
Applicability
Target applications for VME backplanes include industrial controls, telecommunications, simulation, high-energy
physics, office automation, and instrumentation systems.
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
74VMEH22501DGGRE4 ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 VMEH22501
SN74VMEH22501DGG ACTIVE TSSOP DGG 48 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 VMEH22501
SN74VMEH22501DGGR ACTIVE TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 VMEH22501
SN74VMEH22501DGVR ACTIVE TVSOP DGV 48 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 85 VK501
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
I TEXAS INSTRUMENTS
PACKAGE OPTION ADDENDUM
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Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
I TEXAS INSTRUMENTS REEL DIMENSIONS TAPE DIMENSIONS 7 “K0 '«m» Reel Diame|er AD Dimension deswgned to accommodate the componem wwdlh E0 Dimension desxgned to accommodate the componenl \ength KO Dimenslun deswgned to accommodate the componem thickness 7 w OveraH wwdm loe earner cape i p1 Pitch between successwe cavuy cemers f T Reel Width (W1) QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O D O O D O Sprockemoles ,,,,,,,,,,, ‘ User Direcllon 0' Feed Pockel Quadrams
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74VMEH22501DGGR TSSOP DGG 48 2000 330.0 24.4 8.6 13.0 1.8 12.0 24.0 Q1
SN74VMEH22501DGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
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I TEXAS INSTRUMENTS TAPE AND REEL BOX DIMENSIONS
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74VMEH22501DGGR TSSOP DGG 48 2000 367.0 367.0 45.0
SN74VMEH22501DGVR TVSOP DGV 48 2000 853.0 449.0 35.0
PACKAGE MATERIALS INFORMATION
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17 i Gage Plane 0,15 7|,20MAX 0,? PINS N 14 1s 20 24 as 43 56 DIM AMAX 3‘70 3.70 5‘10 5.10 700 9,00 11,40 AMIN 350 3,50 400 4,90 7‘70 9,50 11,20 407325| /E 03/00 *5 TEXAS INSTRUMENTS p057 omca aox $55303 - DALLAS IEXAS 752s5
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
J ‘ .: 1:! E 4 T I-EIII :f f E l E 4 0° 5 X7 7 L7 ' TEXAS
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PACKAGE OUTLINE
C
8.3
7.9 TYP
1.2
1.0
46X 0.5
48X 0.27
0.17
2X
11.5
(0.15) TYP
0 - 8 0.15
0.05
0.25
GAGE PLANE
0.75
0.50
A
12.6
12.4
NOTE 3
B6.2
6.0
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
148
0.08 C A B
25
24
PIN 1 ID
AREA
SEATING PLANE
0.1 C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 1.350
$E§$$fi§$fifim fl%%mgmififimgm r:r A
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EXAMPLE BOARD LAYOUT
(7.5)
0.05 MAX
ALL AROUND 0.05 MIN
ALL AROUND
48X (1.5)
48X (0.3)
46X (0.5)
(R0.05)
TYP
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
SYMM
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
1
24 25
48
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
www.ti.com
EXAMPLE STENCIL DESIGN
(7.5)
46X (0.5)
48X (0.3)
48X (1.5)
(R0.05) TYP
4214859/B 11/2020
TSSOP - 1.2 mm max heightDGG0048A
SMALL OUTLINE PACKAGE
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
SYMM
SYMM
1
24 25
48
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
O i H1HHHHHHHHHHHHHHHHHHHHHHZHA % IIIIIIIIIIII 1,20MAX ii ED; ‘V' TEXAS INSTRUMENTS POST OFFICE BOX 655303 ' DA
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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