S1D13781 Brief Datasheet by Epson Electronics America Inc-Semiconductor Div
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S1D13781 Features
X94A-C-001-01 1
Revision 1.1
GRAPHICS
S1D13781
S1D13781 WQVGA Graphics Controller August 2009
The S1D13781 is a simple, multi-purpose Graphics LCD Controller with 384KByte embedded SRAM display
buffer which supports both RGB interface TFT and CSTN panels. The S1D13781 supports most popular CPU
interfaces in both 8/16-bit and Direct/Indirect variations. The embedded display buffer allows WQVGA up to
480x272 at 24bpp or 800x480 8bpp for single layer display, or 480x272 at 16bpp (Main Layer) and 480x272 at
8bpp (PIP Layer) for two layer display.
The S1D13781’s combination of multiple CPU interfaces and display interface types offers a versatile, yet easy to
develop display system. Additionally, it offers Multiple Window support, Transparency and Alpha Blending
functions, as well as 2D BitBLT functions. It is a flexible, low cost, low power, single chip solution designed to meet
the demands of embedded markets such as low end IP phone devices where total system cost and battery life
are major concerns. It’s impartiality to CPU type or operating system also makes it an ideal display solution for a
wide variety of other applications such as Office Automation and Factory Automation applications.
nFEATURES
nSYSTEM BLOCK DIAGRAM
•384KByte Embedded Memory
•Direct and Indirect CPU Interfaces
•8/16-bit data bus width
•SPI CPU interface
•Support for single panel implementation:
- RGB Interface TFT panel
- Color and Monochrome STN
•Programmable resolutions (up to 800x480@8bpp)
and color depth (up to 24 bpp)
•Multiple Window (Layer) support for Main and PIP
•Rotation (Swivel View) 90°/180°/270°
•General Purpose IO Pins
•LUT 256wordx24bitx3pcs for both Main and PIP
layer
•Alpha Blending, Transparency, Flashing
•2D BitBLT
•Software initiated Power Save Mode
•H/PIOVDD: 3.3 or 1.8V, CORE/PLLVDD: 1.5V
•Clocks can be selected from embedded PLL or
digital clock inputs
•Temperature Range: -40° ~ 85°
•Package: QFP100-pin, 0.5mm pin pitch
Host
Control Signals
S1D13781
CPU
TFT, CSTN
S1D13781 Features
Embedded display buffer
2 layer support
Alpha Blending and Transparency
PIP layer Flashing
Programmable PLL
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Revision 1.1 X94A-C-001-01 2
GRAPHICS
S1D13781
nDESCRIPTION
CPU Interface
•Support for most popular CPU interfaces
•Direct/Indirect Addressing
•8/16-bit interface support
•SPI
Display Support
•Single panel implementation can be:
• RGB Interface TFT panel
• Color and Monochrome STN
•Programmable resolutions up to 800x480@8bpp
•Programmable color depths up to 24 bpp
Display Features
•Multiple Window (Layer) support for Main and PIP
•Alpha Blending and Transparency
•PIP Flashing
•LUT 256wordx24bitx3pcs for both Main and PIP
layer
•Rotation (Swivel View) 90°/180°/270°
384KByte Embedded Memory
•Maximum Resolution for WQVGA:
1 layer: 480x272 at 24bpp or
800x480 at 8bpp
2 layer: Main 480x272 at 16bpp and
PIP 480x272 at 8bpp
Miscellaneous
•2D BitBLT
•Internal System Speed: TBD
•Software initiated power save mode
•Multiple General Purpose IO pins
•Flexible clock structure:
• Embedded PLL
• Digital clock inputs
•Operating Temperature Range: -40° ~ 85°
•Low Operating Voltage:
PLL/COREVDD 1.5 volts and
PIO/HIOVDD 3.3 or 1.8 volts
•Package: QFP 100-pin, 0.5mm pin pitch
CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS
• S1D13781 Technical
Documentation • CPU Independent
Software Utilities • S1D13781 Evaluation
Boards • Royalty Free source level
driver code
© SEIKO EPSON CORPORATION 2007. All rights reserved.
Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You
may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies
described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
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