UDA1341TS Datasheet by NXP USA Inc.

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“WWW“ BITSTREAM CONVERS‘ON
DATA SHEET
Product specification
Supersedes data of 2001 Jun 29 2002 May 16
INTEGRATED CIRCUITS
UDA1341TS
Economy audio CODEC for
MiniDisc (MD) home stereo and
portable applications
2002 May 16 2
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
CONTENTS
1 FEATURES
1.1 General
1.2 Multiple format data interface
1.3 DAC digital sound processing
1.4 Advanced audio configuration
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 System clock
7.2 Pin compatibility
7.3 Analog front end
7.4 Programmable Gain Amplifier (PGA)
7.5 Analog-to-Digital Converter (ADC)
7.6 Digital Automatic Gain Control (AGC)
7.7 AGC status detection
7.8 Digital mixer
7.9 Decimation filter (ADC)
7.10 Overload detection (ADC)
7.11 Mute (ADC)
7.12 Interpolation filter (DAC)
7.13 Peak detector
7.14 Quick mute
7.15 Noise shaper (DAC)
7.16 Filter Stream Digital-to-Analog Converter
(FSDAC)
7.17 Multiple format input/output interface
7.18 L3-interface
7.19 Address mode
7.20 Data transfer mode
7.21 Programming the sound processing and other
features
7.21.1 STATUS control
7.21.2 DATA0 direct control
7.21.3 DATA0 extended programming registers
7.21.4 DATA1 control
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 DC CHARACTERISTICS
11 AC CHARACTERISTICS (ANALOG)
12 AC CHARACTERISTICS (DIGITAL)
13 APPLICATION INFORMATION
14 PACKAGE OUTLINE
15 SOLDERING
15.1 Introduction to soldering surface mount
packages
15.2 Reflow soldering
15.3 Wave soldering
15.4 Manual soldering
15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
16 DATA SHEET STATUS
17 DISCLAIMERS
“WWW” BITSTREAM CONVERSION
2002 May 16 3
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
1 FEATURES
1.1 General
Low power consumption
3.0 V power supply
256fs, 384fs or 512fs system clock frequencies (fsys)
Small package size (SSOP28)
Partially pin compatible with UDA1340M and
UDA1344TS
Fully integrated analog front end including digital AGC
ADC plus integrated high-pass filter to cancel DC offset
ADC supports 2 V (RMS value) input signals
Overload detector for easy record level control
Separate power control for ADC and DAC
No analog post filter required for DAC
Easy application
Functions controllable via L3-interface.
1.2 Multiple format data interface
I2S-bus, MSB-justified and LSB-justified format
compatible
Three combinational data formats with MSB data output
and LSB 16, 18 or 20 bits data input
1fs input and output format data rate.
1.3 DAC digital sound processing
Digital dB-linear volume control (low microcontroller
load)
Digital tone control, bass boost and treble
Digital de-emphasis for 32, 44.1 or 48 kHz audio sample
frequencies (fs)
Soft mute.
1.4 Advanced audio configuration
DAC and ADC polarity control
Two channel stereo single-ended input configuration
Microphone input with on-board PGA
Optional differential input configuration for enhanced
ADC sound quality
Stereo line output (under microcontroller volume
control)
Digital peak level detection
High linearity, dynamic range and low distortion.
2 GENERAL DESCRIPTION
The UDA1341TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-Analog Converter (DAC)
with signal processing features employing bitstream
conversion techniques. Its fully integrated analog front
end, including Programmable Gain Amplifier (PGA) and a
digital Automatic Gain Control (AGC). Digital Sound
Processing (DSP) featuring makes the device an excellent
choice for primary home stereo MiniDisc applications, but
by virtue of its low power and low voltage characteristics it
is also suitable for portable applications such as MD/CD
boomboxes, notebook PCs and digital video cameras.
The UDA1341TS is similar to the UDA1340M and the
UDA1344TS but adds features such as digital mixing of
two input signals and one channel with a PGA and a digital
AGC.
The UDA1341TS supports the I2S-bus data format with
word lengths of up to 20 bits, the MSB-justified data format
with word lengths of up to 20 bits, the LSB-justified serial
data format with word lengths of 16, 18 and 20 bits and
three combinations of MSB data output combined with
LSB 16, 18 and 20 bits data input. The UDA1341TS has
DSP features in playback mode like de-emphasis, volume,
bass boost, treble and soft mute, which can be controlled
via the L3-interface with a microcontroller.
3 ORDERING INFORMATION
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
UDA1341TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
2002 May 16 4
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
4 QUICK REFERENCE DATA
Notes
1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 kΩ is used in series
with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS).
2. The ADC input signal scales inversely proportional with the power supply voltage.
3. The DAC output voltage scales linear with the DAC analog supply voltage.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDDA(ADC) ADC analog supply voltage 2.4 3.0 3.6 V
VDDA(DAC) DAC analog supply voltage 2.4 3.0 3.6 V
VDDD digital supply voltage 2.4 3.0 3.6 V
IDDA(ADC) ADC analog supply current operation mode 12.5 mA
ADC power-down 6.0 mA
IDDA(DAC) DAC analog supply current operation mode 7.0 mA
DAC power-down 50 −μA
IDDD digital supply current operation mode 7.0 mA
Tamb operating ambient temperature 20 +85 °C
Analog-to-digital converter
Vi(rms) input voltage (RMS value) notes 1 and 2 1.0 V
(THD + N)/S total harmonic distortion-plus-noise
to signal ratio
stand-alone mode
0dB −−85 80 dB
60 dB; A-weighted −−37 33 dB
double differential mode
0dB −−90 85 dB
60 dB; A-weighted −−40 36 dB
S/N signal-to-noise ratio Vi= 0 V; A-weighted
stand-alone mode 97 dB
double differential mode 100 dB
αcs channel separation 100 dB
Programmable gain amplifier
(THD + N)/S total harmonic distortion-plus-noise
to signal ratio
1kHz; f
s= 44.1 kHz
0dB −−85 dB
60 dB; A-weighted −−37 dB
S/N signal-to-noise ratio Vi= 0 V; A-weighted 95 dB
Digital-to-analog converter
Vo(rms) output voltage (RMS value) supply voltage = 3 V; note 3 900 mV
(THD+N)/S total harmonic distortion-plus-noise
to signal ratio
0dB −−91 86 dB
60 dB; A-weighted −−40 dB
S/N signal-to-noise ratio code = 0; A-weighted 100 dB
αcs channel separation 100 dB
UDA1341TS DIGITAL AGC DIGITAL MIXER DEcIMATIoN FILTEFI DATAO ECK DIGITAL INTERFACE ws DATAI DSP FEATURES oMuTE INTERPOLATION FILTER NOISE SHAPER Vrel \IOUTL 25 VDDAIDAC) Fig.1 BIock diagram. 27 VssA
2002 May 16 5
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
5 BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MGR427
ADC2
PGA PGA
6 8
18
16
17
19
25
12
15
14
13
9
VINL2
VSSD
VDDD
DATAO
BCK
WS
DATAI
VOUTL
27
24
26 VOUTR
SYSCLK
L3DATA
L3CLOCK
L3MODE
OVERFL
VINR2
10 11
DECIMATION FILTER
DIGITAL MIXER
DIGITAL AGC
DIGITAL INTERFACE L3-BUS
INTERFACE
PEAK
DETECTOR
ADC2
DAC
VSSA(DAC)
VDDA(DAC)
DAC
INTERPOLATION FILTER
NOISE SHAPER
DSP FEATURES
20 TEST1
21 TEST2
31
VDDA(ADC) VSSA(ADC)
75
VADCP VADCN
UDA1341TS 22 AGCSTAT
23
QMUTE
28
Vref
ADC1
0 dB/6 dB
SWITCH 0 dB/6 dB
SWITCH
2 4
VINL1 VINR1
ADC1
33333333333333 O EEEEEEEEEEEEEE 33333333333333 O EEEEEEEEEEEEEE
2002 May 16 6
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
6 PINNING
SYMBOL PIN DESCRIPTION
VSSA(ADC) 1 ADC analog ground
VINL1 2 ADC1 input left
VDDA(ADC) 3 ADC analog supply voltage
VINR1 4 ADC1 input right
VADCN 5 ADC negative reference voltage
VINL2 6 ADC2 input left
VADCP 7 ADC positive reference voltage
VINR2 8 ADC2 input right
OVERFL 9 decimation filter overflow output
VDDD 10 digital supply voltage
VSSD 11 digital ground
SYSCLK 12 system clock 256fs, 384fs or 512fs
L3MODE 13 L3-bus mode input
L3CLOCK 14 L3-bus clock input
L3DATA 15 L3-bus data input and output
BCK 16 bit clock input
WS 17 word select input
DATAO 18 data output
DATAI 19 data input
TEST1 20 test control 1 (pull-down)
TEST2 21 test control 2 (pull-down)
AGCSTAT 22 AGC status
QMUTE 23 quick mute input
VOUTR 24 DAC output right
VDDA(DAC) 25 DAC analog supply voltage
VOUTL 26 DAC output left
VSSA(DAC) 27 DAC analog ground
Vref 28 ADC and DAC reference voltage
SYMBOL PIN DESCRIPTION
Fig.2 Pin configuration.
handbook, halfpage
VSSA(ADC)
VINL1
VDDA(ADC)
VINR1
VADCN
VINL2
VADCP
VINR2
OVERFL
VDDD
VSSD
SYSCLK
L3MODE
L3CLOCK
Vref
VSSA(DAC)
VOUTL
VDDA(DAC)
QMUTE
AGCSTAT
VOUTR
TEST2
TEST1
DATAI
DATAO
WS
BCK
L3DATA
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
UDA1341TS
MGR428
Fig.3 Compatible pins with UDA1340M.
handbook, halfpage
VSSA(ADC)
VINL1
VDDA(ADC)
VINR1
VADCN
VINL2
VADCP
VINR2
OVERFL
VDDD
VSSD
SYSCLK
L3MODE
L3CLOCK
Vref
VSSA(DAC)
VOUTL
VDDA(DAC)
QMUTE
AGCSTAT
VOUTR
TEST2
TEST1
DATAI
DATAO
WS
BCK
L3DATA
Marked pins are compatible with UDA1340M
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
UDA1341TS
MGR429
2002 May 16 7
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7 FUNCTIONAL DESCRIPTION
7.1 System clock
The UDA1341TS accommodates slave mode only, this
means that in all applications the system devices must
provide the system clock. The system frequency is
selectable. The options are 256fs, 384fs or 512fs.
The system clock must be locked in frequency to the digital
interface signals.
7.2 Pin compatibility
The UDA1341TS is partially pin compatible with the
UDA1340M and UDA1344TS, making an upgrade of a
printed-circuit board from UDA1340M to UDA1341TS
easier. The pins that are compatible with the UDA1340M
are marked in Fig.3.
7.3 Analog front end
The analog front end of the UDA1341TS consists of two
stereo ADCs with a Programmable Gain Amplifier (PGA) in
channel 2. The PGA is intended to pre-amplify a
microphone signal applied to the input channel 2.
Input channel 1 has a selectable 0 or 6 dB gain stage, to
be controlled via the L3-interface. In this way, input signals
of 1 V (RMS value) or 2 V (RMS value) e.g. from a
CD source can be supported using an external resistor of
12 kΩ in series with the input channel 1. The application
modes are given in Table 1.
Table 1 Application modes using input gain stage
Note
1. If there is no need for 2 V (RMS value) input signal
support, the external resistor should not be used.
7.4 Programmable Gain Amplifier (PGA)
The PGA can be set via the L3-interface at the gain
settings: 3, 0, 3, 9, 15, 21 or 27 dB.
7.5 Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1341TS consists of two
3rd-order Sigma-Delta modulators. They have a modified
Ritchie-coder architecture in a differential switched
capacitor implementation. The over-sampling ratio is 128.
7.6 Digital Automatic Gain Control (AGC)
Input channel 2 has a digital AGC to compress the
dynamic range when a microphone signal is applied to
input channel 2. The digital AGC can be switched on and
off via the L3-interface. In the on state the AGC
compresses the dynamic range of the input signal of input
channel 2. Via the L3-interface the user can set the
parameters of the AGC: attack time, decay time and output
level. When the AGC is set off via the L3-interface, the gain
of input channel 2 can be set manually. In this case the
gain of the PGA and digital AGC are combined. The range
of the gain of the input channel 2 is from 3to+60.5dB in
steps of 0.5 dB.
7.7 AGC status detection
The AGCSTAT signal from the digital AGC is HIGH when
the gain level of the AGC is below 8 dB. This signal can be
used to give the PGA a new gain setting via the
L3-interface and to power e.g. a LED.
7.8 Digital mixer
The two stereo ADCs (including the AGC) can be used in
four modes:
ADC1 only mode (for line input); input channel 2 is off
ADC2 only mode, including PGA and digital AGC (for
microphone input); input channel 1 is off
ADC1 + ADC2 mixer mode, including PGA and AGC
ADC1 and ADC2 double differential mode (improved
ADC performance).
Important: In order to prevent crosstalk between the line
inputs no signal should be applied to the microphone input
in the double differential mode.
In all modes (except the double differential mode) a
reference voltage is always present at the input of the
ADC. However, in the double differential mode there is no
reference voltage present at the microphone input.
In the mixer mode, the output signals of both ADCs in
channel 1 and channel 2 (after the digital AGC) can be
mixed with coefficients that can be set via the L3-interface.
The range of the mixer coefficients is from 0 to −∞ dB in
1.5 dB steps.
RESISTOR
(12 kΩ)
INPUT
GAIN
SWITCH MAXIMUM INPUT VOLTAGE
Present 0 dB 2 V (RMS value) input signal;
note 1
Present 6 dB 1 V (RMS value) input signal
Absent 0 dB 1 V (RMS value) input signal
Absent 6 dB 0.5 V (RMS value) input signal
2002 May 16 8
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.9 Decimation filter (ADC)
The decimation from 128fs is performed in two stages.
The first stage realizes 3rd order characteristic,
decimating by 16. The second stage consists of
3 half-band filters, each decimating by a factor of 2.
Table 2 Decimation filter characteristics
7.10 Overload detection (ADC)
This name is convenient but a little inaccurate. In practice
the output is used to indicate whenever that output data, in
either the left or right channel, is bigger than 1dB (actual
figure is 1.16 dB) of the maximum possible digital swing.
If this condition is detected the OVERFL output is forced
HIGH for at least 512fscycles (11.6 ms at fs=44.1kHz).
This time-out is reset for each infringement.
7.11 Mute (ADC)
On recovery from power-down or switching on of the
system clock, the serial data output on pin DATAO is held
at LOW level until valid data is available from the
decimation filter. This time depends on whether the
DC-cancellation filter is selected:
DC cancel off:
; t = 23.2 ms at fs=44.1kHz
DC cancel on:
; t = 279 ms at fs=44.1kHz.
7.12 Interpolation filter (DAC)
The digital filter interpolates from 1fsto 128fs by means of
a cascade of a recursive filter and a Finite Impulse
Response (FIR) filter.
Table 3 Interpolation filter characteristics
7.13 Peak detector
In the playback path a peak level detector is build in.
The position of the peak detection can be set via the
L3-interface to either before or after the sound features.
The peak level detector is implemented as a peak-hold
detector, which means that the highest sound level is hold
until the peak level is read out via the L3-interface. After
read-out the peak level registers are reset.
7.14 Quick mute
A hard mute can be activated via the static pin QMUTE.
When QMUTE is set HIGH, the output signal is instantly
muted to zero. Setting QMUTE to LOW, the mute is
instantly de-activated.
7.15 Noise shaper (DAC)
The 3rd-order noise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise shaping technique allows for high
signal-to-noise ratios. The noise shaper output is
converted into an analog signal using a filter stream
digital-to-analog converter.
ITEM CONDITIONS VALUE
(dB)
Passband ripple 0 to 0.45fs±0.05
Stop band >0.55fs60
Dynamic range 0 to 0.45fs108
Overall gain input channel 1;
0 dB input
1.16
sin x
x
------------
t1024
fs
-------------
=
t12288
fs
----------------
=
ITEM CONDITIONS VALUE
(dB)
Passband ripple 0 to 0.45fs±0.03
Stop band >0.55fs50
Dynamic range 0 to 0.45fs108
2002 May 16 9
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.16 Filter Stream Digital-to-Analog Converter
(FSDAC)
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. A post filter is not needed due to the
inherent filter function of the DAC. On-board amplifiers
convert the FSDAC output current to an output voltage
signal capable of driving a line output.
7.17 Multiple format input/output interface
The UDA1341TS supports the following data formats:
I2S-bus with word length up to 20 bits
MSB-justified serial format with word length up to 20 bits
LSB-justified serial format with word length of
16, 18 or 20 bits
MSB data output with LSB 16, 18 or 20 bits input.
Left and right data-channel words are time multiplexed.
The formats are illustrated in Fig.4.
The UDA1341TS allows for double speed data monitoring
purposes. In this case the sound features bass boost,
treble and de-emphasis cannot be used. However, volume
control and soft-mute can still be controlled. The double
speed monitoring option can be set via the L3-interface.
The bit clock frequency must be 64 times word select
frequency or less, so fBCK 64 ×fWS.
2002 May 16 10
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
han
dbook, full pagewidth
LSB-JUSTIFIED FORMAT 16 BITS
LSB-JUSTIFIED FORMAT 18 BITS
LSB-JUSTIFIED FORMAT 20 BITS
MSB-JUSTIFIED FORMAT
WS LEFT
LEFT
LEFT
LEFT
RIGHT
RIGHT
RIGHT
RIGHT
32
2
215161718 1
1516 1
1321
MSB B2 MSBLSB LSB MSB B2B2
MSB LSBB2
MSB B2 B3 B4
B15
LSB
B17
215161718 1
MSB B2 B3 B4 LSB
B17
2151617181920 1
MSB B2 B3 B4 B5 B6 LSB
B19
2151617181920 1
MSB B2 B3 B4 B5 B6 LSB
B19
21516 1
MSB LSBB2 B15
>=8 >=8
BCK
D
ATA
WS LEFT RIGHT
321321
MSB B2 MSBLSB LSB MSBB2
>=8 >=8
BCK
D
ATA
WS
BCK
D
ATA
WS
BCK
D
ATA
WS
BCK
D
ATA
INPUT FORMAT I2S-BUS
MGG84
1
Fig.4 Serial interface formats.
2002 May 16 11
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.18 L3-interface
The UDA1341TS has a microcontroller input mode. In the
microcontroller mode, all the digital sound processing
features and the system controlling features can be
controlled by the microcontroller.
The controllable features are:
Reset
System clock frequency
Power control
DAC gain switch
ADC input gain switch
ADC/DAC polarity control
Double speed playback
De-emphasis
Volume
Mode switch
Bass boost
Treble
Mute
MIC sensitivity control
AGC control
Input amplifier gain control
Digital mixer control
Peak detection position.
Via the L3-interface the peak level value of the signal in the
DAC path can be read out from the UDA1341TS to the
microcontroller.
The exchange of data and control information between the
microcontroller and the UDA1341TS is accomplished
through a serial hardware L3-interface comprising the
following pins:
L3DATA: microcontroller interface data line
L3MODE: microcontroller interface mode line
L3CLOCK: microcontroller interface clock line.
Information transfer through the microcontroller bus is
organized in accordance with the so called ‘L3’ format, in
which two different modes of operation can be
distinguished: address mode and data transfer mode.
The address mode is required to select a device
communicating via the L3-bus and to define the
destination registers for the data transfer mode.
Data transfer can be in both directions: input to the
UDA1341TS to program its sound processing and system
controlling features and output from the UDA1341TS to
provide the peak level value.
7.19 Address mode
The address mode is used to select a device for
subsequent data transfer and to define the destination
registers. The address mode is characterized by L3MODE
being LOW and a burst of 8 pulses on L3CLOCK,
accompanied by 8 data bits. The fundamental timing is
shown in Fig.5.
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The address of the
UDA1341TS is 000101.
Data bits 0 to 1 indicate the type of the subsequent data
transfer as shown in Table 4.
In the event that the UDA1341TS receives a different
address, it will deselect its microcontroller interface logic.
7.20 Data transfer mode
The selection activated in the address mode remains
active during subsequent data transfers, until the
UDA1341TS receives a new address command.
The fundamental timing of data transfers is essentially the
same as the timing in the address mode and is given in
Fig.6.
Note that ‘L3DATA write’ denotes data transfer from the
microcontroller to the UDA1341TS and ‘L3DATA peak
read’ denotes data transfer in the opposite direction.
The maximum input clock and data rate is 64fs.
All transfers are byte-wise, i.e. they are based on groups
of 8 bits. Data will be stored in the UDA1341TS after the
eighth bit of a byte has been received.
A multibyte transfer is illustrated in Fig.7.
j \ * ‘i‘mLSVA |5u(L3)A4> + ‘CLK(L3)L4> a ‘*‘su1L3}A |cLK(L3)H+‘ *“mmA + LSCLOCK J LTWW, *‘ “’ISMLDDA *‘ ‘+ |h(L3)DA M X X x X x M Fig.5 Twming address mode. 2002 May 16 12
2002 May 16 12
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
Table 4 Selection of data transfer
BIT 1 BIT 0 MODE TRANSFER
0 0 DATA0 direct addressing registers: volume, bass boost, treble, peak detection position,
de-emphasis, mute and mode
extended addressing registers: digital mixer control, AGC control, MIC sensitivity control,
input gain, AGC time constant and AGC output level
0 1 DATA1 peak level value read-out (information from UDA1341TS to microcontroller)
1 0 STATUS reset, system clock frequency, data input format, DC-filter, input gain switch, output gain
switch, polarity control, double speed and power control
1 1 not used
Fig.5 Timing address mode.
handbook, full pagewidth
th(L3)A
th(L3)DA
tsu(L3)DA
Tcy(CLK)(L3)
BIT 0
L3MODE
L3CLOCK
L3DATA BIT 7
MGR431
tCLK(L3)H
tCLK(L3)L
tsu(L3)A
tsu(L3)A
th(L3)A
V k m r fl V HUXXXXXXK \/XXXXX\ ng.7 Mun iiiiiiiiiiiiii
2002 May 16 13
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
Fig.6 Timing for data transfer mode.
handbook, full pagewidth
tstp(L3) tstp(L3)
tsu(L3)D
th(L3)DA tsu(L3)DA th(L3)DA
th(L3)D
Tcy(CLK)L3
BIT 0
L3MODE
L3CLOCK
L3DATA
read
L3DATA
write BIT 7
MGR430
PL0 PL5PL4PL3PL2PL1
tCLK(L3)H
tCLK(L3)L
Fig.7 Multibyte transfer.
handbook, full pagewidth tstp(L3)
address
L3DATA
L3CLOCK
L3MODE
addressdata byte #1 data byte #2 MGR432
2002 May 16 14
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.21 Programming the sound processing and other
features
The sound processing and other feature values are stored
in independent registers.
The first selection of the registers is achieved by the choice
of data type that is transferred. This is performed in the
address mode using bit 0 and bit 1 (see Table 4).
The second selection is performed by the 2 or 3 MSBs of
the data byte (bits 7 and 6 or bits 7, 6 and 5).
The other bits in the data byte (bits 5 to 0 or bits 4 to 0)
represent the value that is placed in the selected registers.
For the UDA1341TS the following modes can be selected:
STATUS
In this mode the features reset, system clock frequency,
data input format, DC-filter, input gain switch, output
gain switch, polarity control, double speed and power
control can be controlled.
DATA0
There are two addressing modes: direct addressing
mode and extended addressing mode.
Direct addressing mode is using the 2 MSB bits of the
data byte. Via this addressing mode the features
volume, bass boost, treble, peak position, de-emphasis,
mute, and mode can be controlled directly.
Extended addressing mode is provided for controlling
the features digital mixer, AGC control, MIC sensitivity,
input gain, AGC time constants, and AGC output level.
An extended address can be set via the EA registers
(3 bits). The data in the extended registers can be set by
writing data to the ED registers (5 bits).
DATA1
In this mode the detected peak level value can be read
out.
Table 5 Default settings
SYMBOL FEATURE SETTING OR VALUE
Status
OGS Output gain switch 0 dB
IGS Input gain switch 0 dB
PAD Polarity of ADC non-inverting
PDA Polarity of DAC non-inverting
DS Double speed single speed
PC Power control ADC and DAC on
Direct control
VC Volume control 0 dB
BB Bass boost 0 dB
TR Treble 0 dB
PP Peak detection position after the tone features
DE De-emphasis no de-emphasis
MT Mute no mute
M Mode switch flat
Extended programming
MA Mixer gain channel 1 6dB
MB Mixer gain channel 2 6dB
MS MIC sensitivity 0 dB
MM Mixer mode switch double differential
AG AGC control disable AGC
AT AGC attack and decay time 11 ms and100 ms
AL AGC output level 9dBFS
2002 May 16 15
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.21.1 STATUS CONTROL
Table 6 Data transfer of type ‘STATUS’
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 REGISTER SELECTED
0 RST SC1 SC0 IF2 IF1 IF0 DC RST = reset
SC = system clock frequency (2 bits)
IF = data input format (3 bits)
DC = DC-filter
1 OGS IGS PAD PDA DS PC1 PC0 OGS = output gain (6 dB) switch
IGS = input gain (6 dB) switch
PAD = polarity of ADC
PDA = polarity of DAC
DS = double speed
PC = power control (2 bits)
7.21.1.1 Reset
A 1-bit value to initialize the L3-registers with the default
settings except system clock frequency.
Table 7 Reset settings
7.21.1.2 System clock frequency
A 2-bit value to select the used external clock frequency.
Table 8 System clock settings
7.21.1.3 DC-filter
A 1-bit value to enable the digital DC-filter.
Table 9 DC-filtering settings
7.21.1.4 Data input format
A 3-bit value to select the data input format.
Table 10 Data input format settings
RST FUNCTION
0no reset
1 reset
SC1 SC0 FUNCTION
0 0 512fs
0 1 384fs
1 0 256fs
1 1 not used
DC FUNCTION
0 no DC-filtering
1 DC-filtering
IF2 IF1 IF0 FUNCTION
000I
2S-bus
0 0 1 LSB-justified 16 bits
0 1 0 LSB-justified 18 bits
0 1 1 LSB-justified 20 bits
1 0 0 MSB-justified
1 0 1 LSB-justified 16 bits input and
MSB-justified output
1 1 0 LSB-justified 18 bits input and
MSB-justified output
1 1 1 LSB-justified 20 bits input and
MSB-justified output
2002 May 16 16
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.21.1.5 Output gain switch
A 1-bit value to control the DAC output gain switch.
The default setting is given in Table 5.
Table 11 Gain switch of DAC settings
7.21.1.6 Input gain switch
A 1-bit value to control the ADC input gain switch.
The default setting is given in Table 5.
Table 12 Gain switch of ADC settings
7.21.1.7 Polarity of ADC
A 1-bit value to control the ADC polarity. The default
setting is given in Table 5.
Table 13 Polarity control of ADC settings
7.21.1.8 Polarity of DAC
A 1-bit value to control the DAC polarity. The default
setting is given in Table 5.
Table 14 Polarity control of DAC settings
7.21.1.9 Double speed
A 1-bit value to enable the double speed playback.
The default setting is given in Table 5.
Table 15 Double speed settings
7.21.1.10 Power control
A 2-bit value to disable the ADC and/or DAC to reduce
power consumption. The default setting is given in Table 5.
Table 16 Power control settings
OGS GAIN OF DAC
00dB
16dB
IGS GAIN OF ADC
00dB
16dB
PAD POLARITY OF ADC
0 non-inverting
1 inverting
PDA POLARITY OF DAC
0 non-inverting
1 inverting
DS FUNCTION
0 single speed playback
1 double speed playback
PC1 PC0 FUNCTION
ADC DAC
00 off off
01 off on
1 0 on off
11 on on
2002 May 16 17
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.21.2 DATA0 DIRECT CONTROL
Table 17 Data transfer of type ‘DATA0’
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 REGISTER SELECTED
0 0 VC5 VC4 VC3 VC2 VC1 VC0 VC = volume control (6 bits)
0 1 BB3 BB2 BB1 BB0 TR1 TR0 BB = bass boost (4 bits)
TR = treble (2 bits)
1 0 PP DE1 DE0 MT M1 M0 PP = peak detection position
DE = de-emphasis (2 bits)
MT = mute
M = mode switch (2 bits)
1 1 0 0 0 EA2 EA1 EA0 EA = extended address (3 bits)
1 1 1 ED4 ED3 ED2 ED1 ED0 ED = extended data (5 bits)
7.21.2.1 Volume control
A 6-bit value to program the left and right channel volume
attenuation. The range is from 0 to −∞ dB in steps of 1 dB.
The default setting is given in Table 5.
Table 18 Volume settings
7.21.2.2 Bass boost
A 4-bit value to program the bass boost settings. The used
set depends on the mode bits. The default setting is given
in Table 5.
Table 19 Bass boost settings
VC5VC4VC3VC2VC1VC0 VOLUME
(dB)
000000 0
000001 0
000010 1
000011 2
:::::: :
111011 58
111100 59
111101 60
111110 −∞
111111 −∞
BB3 BB2 BB1 BB0
BASS BOOST
FLAT
(dB) MIN.
(dB) MAX.
(dB)
0000 0 0 0
0001 0 2 2
0010 0 4 4
0011 0 6 6
0100 0 8 8
0101 0 10 10
0110 0 12 12
0111 0 14 14
1000 0 16 16
1001 0 18 18
1010 0 18 20
1011 0 18 22
1100 0 18 24
1101 0 18 24
1110 0 18 24
2002 May 16 18
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.21.2.3 Treble
A 2-bit value to program the treble setting. The used set
depends on the mode bits. The default setting is given in
Table 5.
Table 20 Treble settings
7.21.2.4 Peak detection position
A 1-bit value to control the position of the peak level
detector in the signal processing path. The default setting
is given in Table 5.
Table 21 Peak detection position settings
7.21.2.5 De-emphasis
A 2-bit value to enable the digital de-emphasis filter.
The default setting is given in Table 5.
Table 22 De-emphasis settings
7.21.2.6 Mute
A 1-bit value to enable the digital mute. The default setting
is given in Table 5.
Table 23 Mute settings
7.21.2.7 Mode
A 2-bit value to program the mode of the sound processing
filters of bass boost and treble. The default setting is given
in Table 5.
Table 24 Mode filter switch settings
TR1 TR0
TREBLE
FLAT
(dB) MIN.
(dB) MAX.
(dB)
00 0 0 0
01 0 2 2
10 0 4 4
11 0 6 6
PP FUNCTION
0 before tone features
1 after tone features
DE1 DE0 FUNCTION
0 0 no de-emphasis
0 1 de-emphasis: 32 kHz
1 0 de-emphasis: 44.1 kHz
1 1 de-emphasis: 48 kHz
MT FUNCTION
0no mute
1mute
M1 M0 FUNCTION
00flat
0 1 minimum
1 0 minimum
1 1 maximum
2002 May 16 19
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.21.3 DATA0 EXTENDED PROGRAMMING REGISTERS
Table 25 Extended control registers
EA2 EA1 EA0 ED4 ED3 ED2 ED1 ED0 REGISTER SELECTED
0 0 0 MA4 MA3 MA2 MA1 MA0 MA = mixer gain channel 1 (5 bits)
0 0 1 MB4 MB3 MB2 MB1 MB0 MB = mixer gain channel 2 (5 bits)
0 1 0 MS2 MS1 MS0 MM1 MM0 MS = MIC sensitivity (3 bits)
MM = mixer mode (2 bits)
100AG00IG1IG0AG=AGC control
IG = input amplifier gain channel 2 (2 bits)
1 0 1 IG6 IG5 IG4 IG3 IG2 IG = input amplifier gain channel 2 (5 bits)
1 1 0 AT2 AT1 AT0 AL1 AL0 AT = AGC time constant (3 bits)
AL = AGC output level (2 bits)
Programming via extended addressing is done by first
sending a DATA0 data byte EA (3 bits) which specifies the
addresses of the extended register followed by a DATA0
data byte which specifies the contents of the extended
data register (5 bits). The EA extended addresses and
names of the extended data registers are given in
Table 25.
7.21.3.1 Mixer gain control
Two 5-bit values to program the channel 1 (MA) and
channel 2 (MB) coefficients in the mixer mode. The range
is from 0 to −∞ dB in steps of 1.5 dB. The default settings
are given in Table 5.
Table 26 Mixer gain control channel 1 and channel 2
settings
7.21.3.2 MIC sensitivity
A 3-bit value to program eight gain settings of the
microphone amplifier. These settings are valid only when
AGC control is enabled and not in the double differential
mode. The default setting is given in Table 5.
Table 27 MIC sensitivity settings
MA4
MB4 MA3
MB3 MA2
MB2 MA1
MB1 MA0
MB0 MIXER GAIN
(dB)
00000 0
00001 1.5
00010 3.0
::::: :
11101 43.5
11110 45.0
11111 −∞
MS2 MS1 MS0 MIC AMPLIFIER GAIN
(dB)
000 3
001 0
010 +3
011 +9
100 +15
101 +21
110 +27
1 1 1 not used
2002 May 16 20
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.21.3.3 Mixer mode
A 2-bit value to program the mode of the digital mixer.
There are four modes: double differential, input channel 1
select, input channel 2 select and digital mixer mode.
The default setting is given in Table 5.
Table 28 Mixer mode switch settings
7.21.3.4 AGC control
A 1-bit value to enable the AGC input. The default setting
is given in Table 5.
Table 29 AGC control settings
7.21.3.5 AGC output level
A 2-bit value to program the AGC output level. The default
setting is given in Table 5.
Table 30 AGC output level settings
7.21.3.6 Input channel 2 amplifier gain
A 7-bit value to program the input channel 2 amplifier gain.
The range is from 3 to +60.5 dB in steps of 0.5 dB. These
settings are only valid when AGC control is disabled and
not valid in the double differential mode.
Table 31 Input channel 2 amplifier gain settings
7.21.3.7 AGC time constant
A 3-bit value to program the attack and the decay
parameters of the digital AGC. The default setting is given
in Table 5.
Table 32 AGC time constant settings
MM1 MM0 FUNCTION
0 0 double differential mode
0 1 input channel 1 select (input channel 2 off)
1 0 input channel 2 select (input channel 1 off)
1 1 digital mixer mode
(input 1 ×MA + input 2 ×MB)
AG FUNCTION
0 disable AGC: manual gain setting through
IG (7 bits)
1 enable AGC: gain control with manual MIC
sensitivity setting
AL1 AL0 OUTPUT LEVEL
(dB FS)
00 9.0
01 11.5
10 15.0
11 17.5
IG6 IG5 IG4 IG3 IG2 IG1 IG0
INPUT
CHANNEL 2
AMPLIFIER
GAIN
(dB)
0000000 3.0
0000001 2.5
0000010 2.0
0000011 1.5
0000100 1.0
0000101 0.5
0000110 0.0
::::::: :
1111101 59.5
1111110 60.0
1111111 60.5
AT2 AT1 AT0 ATTACK TIME
(ms) DECAY TIME
(ms)
000 11 100
001 16 100
010 11 200
011 16 200
100 21 200
101 11 400
110 16 400
111 21 400
2002 May 16 21
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
7.21.4 DATA1 CONTROL
Table 33 Data transfer of type ‘DATA1’
7.21.4.1 Peak level value
A 6-bit value to indicate the peak level value of the playback data. The largest value of the left and right channel data in
the playback signal path is held since the last read-out of the microcontroller.
Table 34 Peak level read-out data
Notes
1. Peak value (dB) = (Peak level 63.5) ×5×log 2.
2. For peak data >010011, the error in the peak value is
3. For peak data <010100, the error is larger due to limited bit length.
BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 READ-OUT DATA
PL5 PL4 PL3 PL2 PL1 PL0 peak level value (6 bits)
PL5 PL4 PL3 PL2 PL1 PL0 PEAK
VALUE(1)
(dB)
000000−∞
000001n.a.
000010n.a.
00001190.31
000100n.a.
000101n.a.
000110n.a.
00011184.29
:::::::
010011note2
010100note3
:::::::
1111012.87
1111101.48
1111110.00
<11 2log×
4
--------------------------
2002 May 16 22
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); VDDD =V
DDA = 3 V; all voltages measured with
respect to ground; Tamb =25°C; unless otherwise specified.
Notes
1. All VDD and VSS connections must be made to the same power supply.
2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor.
3. Equivalent to discharging a 200 pF capacitor via a 2.5 μH series inductor.
4. DAC operation cannot be guaranteed after a short-circuit has occurred.
9 THERMAL CHARACTERISTICS
10 DC CHARACTERISTICS
VDDD =V
DDA =3V; T
amb =25°C; RL=5kΩ; all voltages measured with respect to ground (pins 1, 11 and 27); unless
otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDD supply voltage note 1 5.0 V
Txtal(max) maximum crystal temperature 150 °C
Tstg storage temperature 65 +125 °C
Tamb operating ambient temperature 20 +85 °C
Ves electrostatic handling note 2 2000 +2000 V
note 3 250 +250 V
Ilu(prot) latch-up protection current Tamb =125°C; VDD = 3.6 V 200 mA
Isc(DAC) DAC short-circuit current: Tamb =0°C; VDD = 3.0 V;
note 4
output short-circuited to VSSA(DAC) 482 mA
output short-circuited to VDDA(DAC) 346 mA
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to ambient in free air 90 K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDDA(ADC) ADC analog supply voltage note 1 2.4 3.0 3.6 V
VDDA(DAC) DAC analog supply voltage note 1 2.4 3.0 3.6 V
VDDD digital supply voltage note 1 2.4 3.0 3.6 V
IDDA(ADC) ADC analog supply current operation mode 12.5 mA
ADC power-down 6.0 mA
IDDA(DAC) DAC analog supply current operation mode 7.0 mA
DAC power-down 50 −μA
IDDD digital supply current operation mode 7.0 mA
DAC power-down 4.0 mA
ADC power-down 3.0 mA
2002 May 16 23
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
Notes
1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit.
2. When higher capacitive loads (above 50 pF) must be driven then a resistor of 100 Ω must be connected in series
with the DAC output in order to prevent oscillations in the output operational amplifier.
Digital input pins
VIH HIGH-level input voltage 0.8VDDD VDDD +0.5 V
VIL LOW-level input voltage 0.5 0.2VDDD V
|ILI| input leakage current −−10 μA
Ciinput capacitance −−10 pF
Digital output pins
VOH HIGH-level output voltage IOH =2mA 0.85V
DDD −− V
VOL LOW-level output voltage IOL =2mA −−0.4 V
Analog-to-digital converter
VADCP positive reference voltage VDDA V
VADCN negative reference voltage 0.0 0.0 0.0 V
Ro(ref) V
ref reference output resistance pin 28 24 kΩ
Riinput resistance measured at 1 kHz
stand-alone mode 12.5 kΩ
double differential mode 6.25 kΩ
Ciinput capacitance 20 pF
Programmable gain amplifier (input channel 2)
Riinput resistance microphone mode 12.5 kΩ
double differential mode >1 MΩ
Digital-to-analog converter
Rooutput resistance 0.13 3.0 Ω
Io(max) maximum output current (THD + N)/S < 0.1% 0.22 mA
RLload resistance 3 −− kΩ
CLload capacitance note 2 −−50 pF
Reference voltage
Vref reference voltage with respect to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 May 16 24
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
11 AC CHARACTERISTICS (ANALOG)
VDDD =V
DDA =3V; f
i= 1 kHz; fs=44.1kHz; T
amb =25°C; RL=5kΩ; all voltages measured with respect to ground
(pins 1, 11 and 27); unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Analog-to-digital converter
Vi(rms) input voltage (RMS value) notes 1 and 2 1.0 V
ΔViunbalance between
channels
0.1 dB
(THD + N)/S total harmonic
distortion-plus-noise to
signal ratio
stand-alone mode
0dB −−85 80 dB
60 dB; A-weighted −−37 33 dB
double differential mode
0dB −−90 85 dB
60 dB; A-weighted −−40 36 dB
S/N signal-to-noise ratio Vi= 0 V; A-weighted
stand-alone mode 97 dB
double differential mode 100 dB
αcs channel separation 100 dB
PSRR power supply rejection ratio fripple =1kHz;
Vripple(p-p) =30mV
30 dB
Manual gain mode (AGC disabled)
Gmin minimum gain −−3dB
Gmax maximum gain 60.5 dB
Gstep digital gain step 0.5 dB
Programmable gain amplifier
Vi(rms) input voltage (RMS value) at full-scale
3 dB setting 1414 mV
0dB setting 1000 mV
3dB setting 708 mV
9dB setting 355 mV
15 dB setting 178 mV
21 dB setting 89 mV
27 dB setting 44 mV
(THD + N)/S total harmonic
distortion-plus-noise to
signal ratio
at 0 dB
3 dB setting −−75 dB
0dB setting −−85 dB
3dB setting −−85 dB
9dB setting −−85 dB
15 dB setting −−80 dB
21 dB setting −−75 dB
27 dB setting −−75 dB
2002 May 16 25
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
Notes
1. The ADC inputs can be used in a 2 V (RMS value) input signal configuration when a resistor of 12 kΩ is used in series
with the inputs and 1 or 2 V (RMS value) input signal operation can be selected via the Input Gain Switch (IGS).
2. The ADC input signal scales inversely proportional with the power supply voltage.
3. The DAC output voltage scales linear with the DAC analog supply voltage.
(THD + N)/S total harmonic
distortion-plus-noise to
signal ratio
at 60 dB; A-weighted
3 dB setting tbf dB
0dB setting −−37 dB
3dB setting tbf dB
9dB setting tbf dB
15 dB setting tbf dB
27 dB setting tbf dB
Digital-to-analog converter
Vo(rms) output voltage (RMS value) note 3 900 mV
ΔVounbalance between
channels
0.1 dB
(THD + N)/S total harmonic
distortion-plus-noise to
signal ratio
0dB −−91 86 dB
60 dB; A-weighted −−40 dB
S/N signal-to-noise ratio code = 0; A-weighted 100 dB
αcs channel separation 100 dB
PSRR power supply rejection ratio fripple =1kHz;
Vripple(p-p) =100mV
50 dB
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 May 16 26
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
12 AC CHARACTERISTICS (DIGITAL)
VDDD =V
DDA = 2.7 to 3.6 V; Tamb =20 to +85 °C; all voltages measured with respect to ground (pins 1, 11 and 27);
unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock timing (see Fig.8)
Tsys clock cycle time fsys =256f
s78 88 131 ns
fsys =384f
s52 59 87 ns
fsys =512f
s39 44 66 ns
tCWL LOW-level pulse width fsys < 19.2 MHz 0.30Tsys 0.70Tsys ns
fsys 19.2 MHz 0.40Tsys 0.60Tsys ns
tCWH HIGH-level pulse width fsys < 19.2 MHz 0.30Tsys 0.70Tsys ns
fsys 19.2 MHz 0.40Tsys 0.60Tsys ns
Serial input/output data timing (see Fig.9)
Tcy bit clock cycle time 300 −−ns
tBCK(H) bit clock HIGH time 100 −−ns
tBCK(L) bit clock LOW time 100 −−ns
trrise time −−20 ns
tffall time −−20 ns
ts;DATI data input set-up time 20 −−ns
th;DATI data input hold time 0 −−ns
td;DATO(BCK) data output delay time
(from BCK falling edge)
−−80 ns
td;DATO(WS) data output delay time
(from WS edge)
MSB-justified format −−80 ns
th;DATO data output hold time 0 −−ns
ts;WS word select set-up time 20 −−ns
th;WS word select hold time 10 −−ns
Microcontroller L3-interface timing (see Figs 5 and 6)
Tcy(CLK)(L3) L3CLOCK 500 −−ns
tCLK(L3)H L3CLOCK HIGH time 250 −−ns
tCLK(L3)L L3CLOCK LOW time 250 −−ns
tsu(L3)A L3MODE set-up time addressing mode 190 −−ns
th(L3)A L3MODE hold time addressing mode 190 −−ns
tsu(L3)D L3MODE set-up time data transfer mode 190 −−ns
th(L3)D L3MODE hold time data transfer mode 190 −−ns
tsu(L3)DA L3DATA set-up time data transfer and
addressing mode
190 −−ns
th(L3)DA L3DATA hold time data transfer and
addressing mode
30 −−ns
tstp(L3) L3MODE halt time 190 −−ns
2002 May 16 27
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
Fig.8 System clock timing.
handbook, full pagewidth
MGL443
tCWH
tCWL
Tsys
Fig.9 Serial interface timing.
handbook, full pagewidth
MGG840
WS
BCK
DATAO
DATAI
tf
trth;WS ts;WS
tBCK(H)
tBCK(L)
Tcy
th;DATO
ts;DATI th;DATI
td(DATO)(BCK)
td(DATO)(WS)
. mafiF mav) law) nsv» 1—; l , P 4117 % mnnF (ssv) VSSAMDC) VDDNADC) ‘ a 5 gym,“ Fm svscm ‘2 am $47“ m mm 1” 7m m ‘5 7%” mm ‘9 uvevfluw OVERFL 9 ”a; ‘— m . Win 2 m; ’ [‘EV) UDAIJMTS C0 V‘NRV 4 F7 i 4w , us w i . )3—“7 23 owa , 22 AGCSTAI LEMODE ‘3 L3CLOCK u a g LSDATA ‘5 2n TESU 27 25 VSSMDACV VDDAIDACV 4H7 v41? Mam: Fig.1!) Application diagram. 2002 May 16 2B
2002 May 16 28
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
13 APPLICATION INFORMATION
Fig.10 Application diagram.
handbook, full pagewidth
MGR433
47 Ω
R30
C11
100 μF
(16 V)
C12
100 μF
(16 V)
VDDA
VDDD
L1
BLM32A07
BLM32A07
L2
+3 V
ground
1
VSSA(ADC)
UDA1341TS
12
28
SYSCLK
Vref
10
35711
VDDD
VDDA(ADC) VADCN VADCP VSSD
system
clock
18
DATAO
16
BCK
17
WS
overflow
flag 9
OVERFL
C1
47 μF
(16 V)
2
VINL1
26 VOUTL R23
100 Ω
R22
10 kΩ
24 VOUTR R26
100 Ω
R27
10 kΩ
C4
47 μF
(16 V)
4
VINR1
19
DATAI
13
L3MODE
14
L3CLOCK
15
L3DATA
100 nF
(63 V)
R21
1 Ω
C2
100 μF
(16 V)
C25
100 nF
(63 V)
C21
VDDA
C3
47 μF
(16 V)
C8
47 μF
(16 V)
C5
47 μF
(16 V)
C22
100 nF
(63 V)
23 QMUTE
22 AGCSTAT
21 TEST2
20 TEST1
100 nF
(63 V)
R28
1 Ω
C9
100 μF
(16 V)
C29
VDDD
VDDA(DAC)
VSSA(DAC)
25
27
R29
1 Ω
C10
100 μF
(16 V)
C27
100 nF
(63 V)
VDDA
left
output
right
output
left
line input
right
C6
47 μF
(16 V)
6
VINL2
C7
47 μF
(16 V)
8
VINR2
left
MIC input
right
HHHHH DIMENSIONS (mm avenue m 9 al HHHHHHH + 4L e w E UNIT A. A, A3 12,, c Dm E“1 9 NE L LP a v 021 nae nan 10A 54 79 103 09 "V“ 005 025 one 100 52 “55 7e ‘25 063 07 02 Note 1 wasuc m mam prmmsmns a! a 2 mm maxwmum perslde are m mcmaea 0."qu REFERENCES EURO ““5”" IEc JEDEC JEITA PRWE SOTSAH M07150 1:} © 2002 May 16 29
2002 May 16 29
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
14 PACKAGE OUTLINE
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 10.4
10.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 1.1
0.7 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT341-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
114
28 15
0.25
y
pin 1 index
0 2.5 5 mm
scale
S
SOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341
-1
A
max.
2
2002 May 16 30
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
15 SOLDERING
15.1 Introduction to soldering surface mount
packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
15.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215to250°C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
15.3 Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
For packages with leads on two sides and a pitch (e):
larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2002 May 16 31
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your NXP Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS
not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
2002 May 16 32
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
16 DATA SHEET STATUS
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
17 DISCLAIMERS
Limited warranty and liability Information in this
document is believed to be accurate and reliable.
However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cumulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditions of commercial
sale of NXP Semiconductors.
Right to make changes NXP Semiconductors
reserves the right to make changes to information
published in this document, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use NXP Semiconductors products are
not designed, authorized or warranted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at
the customer’s own risk.
Applications Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as
for the planned application and use of customer’s third
party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related
to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications
or products, or the application or use by customer’s third
party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applications and the products or of
the application or use by customer’s third party
customer(s). NXP does not accept any liability in this
respect.
2002 May 16 33
NXP Semiconductors Product specification
Economy audio CODEC for MiniDisc (MD)
home stereo and portable applications UDA1341TS
Limiting values Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratings only and
(proper) operation of the device at these or any other
conditions above those given in the Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Terms and conditions of commercial sale NXP
Semiconductors products are sold subject to the general
terms and conditions of commercial sale, as published at
http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an
individual agreement is concluded only the terms and
conditions of the respective agreement shall apply. NXP
Semiconductors hereby expressly objects to applying the
customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control This document as well as the item(s)
described herein may be subject to export control
regulations. Export might require a prior authorization from
national authorities.
Quick reference data The Quick reference data is an
extract of the product data given in the Limiting values and
Characteristics sections of this document, and as such is
not complete, exhaustive or legally binding.
Non-automotive qualified products Unless this data
sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified products in automotive equipment or
applications.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own risk, and (c) customer fully indemnifies
NXP Semiconductors for any liability, damages or failed
product claims resulting from customer design and use of
the product for automotive applications beyond NXP
Semiconductors’ standard warranty and NXP
Semiconductors’ product specifications.
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Printed in The Netherlands 753505/04/pp34 Date of release: 2002 May 16 Document order number: 9397 750 09805

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