IP4337CX18/LF Datasheet by NXP USA Inc.

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1. Product profile
1.1 General description
The IP4337CX18/LF is a 7-channel RC low-pass filter array which is designed to provide
filtering of undesired RF signals in the 800 MHz to 3000 MHz frequency band. In addition,
the IP4337CX18/LF incorporates diodes to provide protection to downstream components
from ElectroStatic Discharge (ESD) voltages as high as ±15 kV.
The IP4337CX18/LF is fabricated using monolithic silicon technology and integrates
7 resistors and 14 diodes in a single Wafer-Level Chip-Scale Package (WLCSP)
measuring 1.96 mm by 1.61 mm (typical). These features make the IP4337CX18/LF ideal
for use in applications requiring the utmost in miniaturization.
1.2 Features
nPb-free, RoHS compliant and free of halogen and antimony (Dark Green compliant)
nIntegrated 7-channel π-type RC filter network
n70 series resistance; 25 pF (typical) capacitance per line
nIntegrated ESD protection withstanding ±15 kV contact discharge, far exceeding
IEC 61000-4-2 level 4
nWLCSP with 0.4 mm pitch
1.3 Applications
nCellular and Personal Communication System (PCS) mobile handsets
nCordless telephones
nWireless data (WAN/LAN) systems
IP4337CX18/LF
7-channel integrated filter network with ESD input protection
to IEC 61000-4-2 level 4
Rev. 02 — 20 August 2009 Product data sheet
0000 O DO 0000 O GO 0000
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 2 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
2. Pinning information
2.1 Pinning
2.2 Pin description
3. Ordering information
Fig 1. Pin configuration IP4337CX18/LF
008aaa185
IP4337CX18/LF
Transparent top view
bump A1
index area 12345
A
B
C
D
Table 1. Pinning
Pin Description
A2 and A5 filter channel 1
A1 and A4 filter channel 2
B1 and B5 filter channel 3
C2 and C5 filter channel 4
C1 and C4 filter channel 5
D2 and D5 filter channel 6
D1 and D4 filter channel 7
A3, B3, C3, D3 ground
B2 and B4 no balls
Table 2. Ordering information
Type number Package
Name Description Version
IP4337CX18/LF WLCSP18 wafer level chip-size package; 18 bumps; 1.96 ×1.61 ×0.61 mm IP4337CX18/LF
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 3 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
4. Functional diagram
5. Limiting values
[1] Device is qualified with 1000 pulses of ±15 kV contact discharges each, according to the IEC 61000-4-2
model and far exceeds the specified level 4 (8 kV contact discharge).
Fig 2. Schematic diagram IP4337CX18/LF
008aaa186
A1, A2, B1, C1,
C2, D1, D2
A3, B3, C3, D3
A4, A5, B5, C4,
C5, D4, D5
Rs(ch)
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VIinput voltage 0.5 +5.5 V
VESD electrostatic discharge voltage all pins to ground
contact discharge [1] 15 +15 kV
air discharge [1] 15 +15 kV
IEC 61000-4-2 level 4;
all pins to ground
contact discharge 8+8kV
air discharge 15 +15 kV
Ich channel current (DC) Tamb =70°C - 33 mA
Pch channel power dissipation continuous power;
Tamb =70°C-60mW
Ptot total power dissipation continuous power;
Tamb =70°C- 250 mW
Tstg storage temperature 55 +150 °C
Treflow(peak) peak reflow temperature 10 s maximum - 260 °C
Tamb ambient temperature 30 +85 °C
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 4 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
6. Characteristics
[1] Guaranteed by design.
Table 4. Channel characteristics
T
amb
=25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Rs(ch) channel series resistance f=0Hz(DC) 52.5 70 87.5
Cch channel capacitance Vbias(DC) = 0 V; f = 1 MHz [1] - 2530pF
VBR breakdown voltage Itest =1mA 6 - 20 V
ILR reverse leakage current per channel; VI= 3.0 V - - 20 nA
Table 5. Frequency characteristics
T
amb
=25
°
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
αil insertion loss 800 MHz<f<3GHz;
Rgen =50; RL=50-20-dB
αct crosstalk attenuation 800 MHz<f<3GHz;
Rgen =50; RL=50-25-dB
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 5 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
7. Application information
7.1 Insertion loss
The insertion loss measurement configuration of a typical 50 NetWork Analyzer (NWA)
system for evaluation of the IP4337CX18/LF is shown in Figure 3.
As an example, the insertion loss of channels between pins A2 and A5, A1 and A4,
B1 and B5, C1 and C4 at frequencies up to 6 GHz is displayed in Figure 4.
The insertion loss is measured with a test PCB utilizing laser drilled micro-via holes that
connect the PCB ground plane to the IP4337CX18/LF ground pins.
Fig 3. Frequency response measurement configuration
(1) Channel 2 (pins A1 and A4).
(2) Channel 1 (pins A2 and A5).
(3) Channel 3 (pins B1 and B5).
(4) Channel 5 (pins C1 and C4).
Fig 4. Measured insertion loss magnitudes
OUT
001aai755
50 50
Vgen
DUT
IN
TEST BOARD
001aaj922
f (MHz)
101103104
102
110
20
30
40
50
60
10
0
s21
(dB)
70
(3)
(4)
(1)
(2)
W \
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 6 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
7.2 Crosstalk
The crosstalk measurement configuration of a typical 50 NWA system for evaluation of
the IP4337CX18/LF is shown in Figure 5.
The measured crosstalk within the IP4337CX18/LF in a 50 NWA system from one
channel to another is shown in Figure 6 for four different pairs of channels. In all cases,
unused connections are terminated with 50 to ground.
Fig 5. Crosstalk measurement configuration
(1) Channels 1 and 2 (pins A2 and A4).
(2) Channels 5 and 7 (pins C1 and D4).
(3) Channels 5 and 1 (pins C1 and A5).
(4) Channels 1 and 7 (pins A2 and D4).
Fig 6. Measured crosstalk between adjacent channels
OUT_2
001aai756
50 50
Vgen
DUT
IN_1
OUT_1IN_2
TEST BOARD 50 50
001aaj923
f (MHz)
101103104
102
110
20
30
40
50
60
10
0
αct
(dB)
70
(1)
(2)
(3)
(4)
Fijaf‘j? D 2) 3/ t‘DJ 1®®+®® 7-, Mg 969 O Q Q GQ O OOWOO S© 69—93—34
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 7 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
8. Package outline
Fig 7. Package outline IP4337CX18/LF (WLCSP18)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
IP4337CX18/LF
ip4337cx18_lf_po
Unit
mm max
nom
min
0.66
0.61
0.56
0.22
0.20
0.18
0.31
0.26
0.21
2.01
1.96
1.91
1.66
1.61
1.56 0.4 1.2
A
Dimensions
WLCSP18: wafer level chip-size package; 18 bumps; 1.96 x 1.61 x 0.61 mm IP4337CX18/LF
A1A2
0.41
bDEee
1
1.6
e2
0 1 2 mm
scale
X
detail X
A
A2
A1
bump A1
index area
BA
D
E
e2
e1
e
e
b
D
C
B
A
54321
09-03-31
09-05-19
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 8 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
9. Soldering of WLCSP packages
9.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package”
and in application note
AN10365 “Surface
mount reflow soldering description”
.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
9.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
9.3 Reflow soldering
Key characteristics in reflow soldering are:
Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 8) than a PbSn process, thus
reducing the process window
Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 6.
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 8.
Table 6. Lead-free process (from J-STD-020C)
Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
maxmum peak tempevaiure = MSL mun damage level mmmum peaklempevamve = mwnwmum samenng (empevamve
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 9 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
For further information on temperature profiles, refer to application note
AN10365
“Surface mount reflow soldering description”
.
9.3.1 Stand off
The stand off between the substrate and the chip is determined by:
The amount of printed solder on the substrate
The size of the solder land on the substrate
The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
9.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
9.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
MSL: Moisture Sensitivity Level
Fig 8. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 10 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”
.
9.3.4 Cleaning
Cleaning can be done after reflow soldering.
10. Abbreviations
11. Revision history
Table 7. Abbreviations
Acronym Description
DUT Device Under Test
ESD ElectroStatic Discharge
LAN Local Area Network
NWA NetWork Analyzer
PCB Printed-Circuit Board
PCS Personal Communication System
RoHS Restriction of Hazardous Substances
WAN Wide Area Network
WLCSP Wafer-Level Chip-Scale Package
Table 8. Revision history
Document ID Release date Data sheet status Change notice Supersedes
IP4337CX18LF_2 20090820 Product data sheet - IP4337CX18LF_1
Modifications: Figure 4: figure title and symbol changed
IP4337CX18LF_1 20090618 Product data sheet - -
IP4337CX18LF_2 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 02 — 20 August 2009 11 of 12
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
12. Legal information
12.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
12.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
12.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
12.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
13. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
founded by PHILIPS
NXP Semiconductors IP4337CX18/LF
7-channel integrated filter network with ESD input protection
© NXP B.V. 2009. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 20 August 2009
Document identifier: IP4337CX18LF_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
14. Contents
1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 General description. . . . . . . . . . . . . . . . . . . . . . 1
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Pinning information. . . . . . . . . . . . . . . . . . . . . . 2
2.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 2
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3
6 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Application information. . . . . . . . . . . . . . . . . . . 5
7.1 Insertion loss . . . . . . . . . . . . . . . . . . . . . . . . . . 5
7.2 Crosstalk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Soldering of WLCSP packages. . . . . . . . . . . . . 8
9.1 Introduction to soldering WLCSP packages . . . 8
9.2 Board mounting . . . . . . . . . . . . . . . . . . . . . . . . 8
9.3 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . 8
9.3.1 Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
9.3.2 Quality of solder joint . . . . . . . . . . . . . . . . . . . . 9
9.3.3 Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
9.3.4 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
10 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 10
11 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10
12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 11
12.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11
12.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
12.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
13 Contact information. . . . . . . . . . . . . . . . . . . . . 11
14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

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