Fiche technique pour EVAL-AD76MUXEDZ Eval Board de Analog Devices Inc.

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Evaluation Board For AD7682/89/99/7949
PulSAR® ADCs
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
FEATURES
Converter and Evaluation Development (EVAL-CED1Z)
compatibility
Versatile analog signal conditioning circuitry
On-board reference, clock oscillator and buffers
PC software for control and data analysis of time and
frequency domain
Stand alone operation
GENERAL DESCRIPTION
The EVAL-AD76MUXCBZ is an evaluation board for the 20
lead PulSAR AD7682, AD7689, AD7699, and AD7949 14-bit
and 16-bit PulSAR analog to digital converter (ADC) family.
These low power, successive approximation register (SAR)
architect-ture ADCs (see Ordering Guide for product list) offer
very high performance with up to 500kSPS throughput rate and
4 – 8 channels. The evaluation board is designed to demonstrate
the ADC's performance and to provide an easy to understand
interface for a variety of system applications. A full description
of the AD7682, AD7689, AD7699, and AD7949 is available in at
www.analog.com and should be consulted when utilizing this
evaluation board.
The evaluation board can be operated as a stand alone or can be
used in conjunction with the Analog Devices EVAL-CED1Z
(CED) USB based data capture board. Since the ADC’s being
evaluated are serial interface only, the EVAL-AD76MUXCBZ
contains the necessary logic to perform serial to parallel
conversion for this interface using the on board FPGA.
On-board components include a high precision band gap
reference, (ADR435), reference buffers, 8-signal conditioning
circuits with an op amp and an FGPA for digital logic. Also
included are separate low drop out regulators for supplying
special voltages of 1.2V and 7V which are not available from the
EVAL-CED1Z.
The board interfaces to the EVAL-CED1Z with a 96-pin DIN
connector. J1, J2 SMB connectors are provided for the low noise
analog signal source for CH0 and CH1 with the remaining
channels (and CH0/1) available on an IDC connector, P1. J3 can
be used for providing an external common (COM) or
configured for any input channel.
Figure 1.Evaluation Board
Analog
Inputs
Signal conditioning Reference Source, COM Select
ADC
FPGA
External COM
(or Input)
P3, 40-Pin IDC
Header
96-Pin EVAL-CED1Z Interface
ANALOG, VDD
POWER
FPGA
POWER
DIGITAL
INTERFACE
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 2 of 26
TABLE OF CONTENTS
Features .............................................................................................. 1
Revision History ............................................................................... 2
Overview........................................................................................ 3
Conversion Control...................................................................... 3
Analog Inputs................................................................................ 3
Serial Interface .............................................................................. 3
Reference ....................................................................................... 3
Power Supplies and Grounding.................................................. 3
Schematics/PCB Layout............................................................... 4
Hardware Setup ............................................................................ 4
Software Installation.....................................................................4
Running the Evaluation Software ..............................................5
Setup Screen...................................................................................5
Configuring the ADC ...................................................................5
DC Testing - Histogram ...............................................................5
AC Testing......................................................................................5
Software Operation.......................................................................8
ADC Configuration......................................................................9
Evaluation Board Schematics and Artwork............................ 15
Ordering Guide .......................................................................... 26
LIST OF FIGURES
Figure 1.Evaluation Board............................................................... 1
Figure 2. Setup Screen...................................................................... 8
Figure 3. Default CFG ..................................................................... 9
Figure 4. CGF Enable/Disable Selection....................................... 9
Figure 5. Input Configuration/Channel Selection........................ 9
Figure 6.BW Select............................................................................ 9
Figure 7. Reference Selection .......................................................... 9
Figure 8. Context Help, User Controls......................................... 10
Figure 9. Histogram Screen ........................................................... 11
Figure 10. Summary .......................................................................12
Figure 11. FFT Spectrum ............................................................... 13
Figure 12 .Oscilloscope.................................................................. 14
Figure 13. Schematic, ADC + Block Diagram............................. 15
Figure 14. Schematic, Supplies...................................................... 16
Figure 15. Schematic, Reference, Buffer, VCM, VBIAS .................... 17
Figure 16. Schematic, AnalogCH0-CH3...................................... 18
Figure 17. Schematic, AnalogCH4-CH7...................................... 19
Figure 18. Schematic, FPGA.......................................................... 20
Figure 19. Schematic, 96-Pin Interface ........................................ 21
Figure 20. Top Side Silk-Screen .................................................... 22
Figure 21. Inner Layer 1................................................................. 22
Figure 22. Ground Plane................................................................ 23
Figure 23. Inner Layer 2................................................................. 23
Figure 24.Inner Layer 3.................................................................. 24
Figure 25. Bottom Layer ................................................................ 24
Figure 26. Bottom Layer ................................................................ 25
LIST OF TABLES
Table 1. Jumper Description............................................................ 6
Table 2.Test Points ............................................................................ 7
Table 3. Bill of Materials for the Connectors .................................7
REVISION HISTORY
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 3 of 26
OVERVIEW
Figure 1 shows the EVAL-AD76MUXCBZ evaluation board.
When used in conjunction with the EVAL-CED1Z, the FPGA,
U6, provides the necessary control signals for conversion and
buffers the ADC serial output data into 16-bit wide transfers.
The evaluation board is a flexible design that enables the user to
choose among many different board configurations, analog
signal conditioning, reference, and different interfaces for
conversion results.
In stand alone operation, the FPGA can be used to buffer the 4-
wire interface via. P3, or directly to the 4 digital interface test
points SDO, SCK, DIN and CNV. For stand alone mode, supply
power to the evaluation board as detailed in the Power Supplies
and Grounding section below.
For FPGA buffered serial interface, supplying power is all that is
necessary. For direct serial connection to the ADC, place a
jumper across P3-39 and P3-40 as P3-40 pulled low places the
FPGA into high impedance.
CONVERSION CONTROL
Conversion start (CNV) controls the sample rate of the ADC
and is the only input needed for conversion; all SAR timing is
internally generated on the ADC. CNV is generated by the gate
array and the frequency is selected with the software.
While the ADC is converting, activity is indicated by the green
LED, CR1. Operating the software in Burst mode as opposed to
Continuous mode, will only light the LED when conversion is
taking place.
For stand alone operation, connect a low jitter source to either
P3-8 or CNV.
ANALOG INPUTS
SMB connectors, J1 and J2, are provided for the ADC input
channels IN0 and IN1 (IN0 only on AD7682). These inputs are
also on the IDC connector P1-2 and P1-4. The remaining inputs
are also on P1-6 through P1-16 (even pins only). J3 can be
configured for providing a common point (COM) for all input
signals or for any analog input IN0-IN7. For using J3 as an
external common point, remove the solder pad (bottom of
PCB) from “COMS to COM” and solder “EXT_COM to COM”
as shown below.
To configure J3 to drive any of the analog input channels,
remove R35 from the left pads (bottom of PCB) and solder it to
the rightmost pads.
The analog input amplifier circuitry U13 – U20 (see schematic -
Figure 13) allows flexible configuration changes such as positive
or negative gain, input range scaling, filtering, addition of a DC
component, use of different op-amp and supplies. The analog
input amplifiers are set as unity gain buffers at the factory. The
supplies are selectable with solder pads VDRV- and VDRV+
and are set for the +7V, -5V range.
Note that when using the unipolar configuration, COMS (P8) is
set to (P8, 2-3) and for bipolar input configuration set to (P8, 1-
2) with pin 1 being the leftmost pin.
SERIAL INTERFACE
The 3-wire serial interface DIN, SCK, and SDO along with CNV
are present on the digital interface test points and FPGA
buffered versions are on the 40-pin IDC connector, P3-2, -4, -6,
-8. When connected to the EVAL-CED1Z and stand alone
(without P3-39 to P3-40 jumper), signals are present at both
locations. With P3-39 to P3-40 connected, these signals are only
present at the test points SDO, SCK DIN and CNV.
REFERENCE
All of the ADCs for this evaluation board can use a precision
trimmed on-chip band gap reference, an on-board precision
ADR435 band gap reference, or an external reference connected
to the EXTREF test point (TP17). The on-chip reference is
enabled or disabled with the software. The on-chip reference
can be set for 2.5V or 4.096V outputs and also includes an
internal buffer, useful for external reference applications. When
using the on-chip reference, remove the jumper on TP7 since
this will overdrive the on-chip reference with the external one.
The default configuration is for on-board ADR435 reference
with a buffered output (P5 2-3), (P6 1-2) and (P7 1-2).
For using an external reference connect to the EXTREF test
point (TP17), select a buffer or not with P6 and select if driving
the ADC REF directly or using the ADC’s internal reference
buffer. When using the internal reference buffer with gain=1,
the maximum output is limited to 4.096V (headroom from 5V
supply).
The default configuration sets the amplifiers output to be at
VREF/2 (mid-scale) from the voltage divider at U1B (VBIAS).
POWER SUPPLIES AND GROUNDING
To attain high resolution performance, the board was designed
to ensure that all digital ground return paths do not cross the
analog ground return paths by connecting the planes together
directly under the converter. Power is supplied to the board
through P3 when using with the EVAL-CED1Z. For stand alone
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EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 4 of 26
operation, the evaluation board requires three diffeetn supplies
and system ground. Connect a supply (7V to 12V) to the analog
supplies tests points +12V and +5VA. Connect -5V to the -5VA
test point. Connect a supply (+3.3V to +5.5V max) to the FPGA
power test point, VDIG.
Connect the power supply GNDs to the GND test point at the
power supplies section of test points making certain the both
analog and digital GNDs are at the same potential.
SCHEMATICS/PCB LAYOUT
The EVAL-AD76MUXCBZ is a 6-layer board carefully laid out
and tested to demonstrate the specific high accuracy
performance of the ADC. Figure 13 through Figure 19 shows
the schematics of the evaluation board. The silkscreens for the
PCB are given in Figure 20 and Figure 22.
HARDWARE SETUP
System Requirements
EVAL-AD7682CBZ, EVAL-AD7689CBZ, EVAL-
AD7699CBZ, EVAL-AD7949CBZ
Evaluation Converter Evaluation and Development board,
EVAL-CED1Z
Enclosed World compatible 7V DC supply
Enlcosed USB to mini USB cable
DC source (low noise for checking different input ranges)
AC source (low distortion)
Band pass filter suitable for 16 or 18 bit testing (value based
on signal frequency)
PC operating Windows XP.
Proceed to the Software Installation section to install the
software. Note: The EVAL-CED1Z board must not be
connected to the PCs USB port until the Software is
installed. The 7V DC supply can be connected however to
check the board has power (green LED lit).
SOFTWARE INSTALLATION
It is recommended to close all Windows applications prior to
installing the software.
System Requirements
PC operating Windows XP.
USB 2.0 (for CED board)
Administrator privileges
CD-ROM –Navigate to Software\CED Version x.x, double click
on setup.exe and follow the instructions on the screen. If
another version of Analog Devices PulSAR Evaluation Software
is present, it may be necessary to remove this. To remove, click
on the Windows Start button, select Control Panel and Add
or Remove Programs. When the list populates, navigate to
Analog Devices High Resolution sampling ADC’s Evaluation
Software or PulSAR Evaluation Software and select Remove.
Website Download
The software versions are also available from the Analog
Devices PulSAR Analog to Digital Converter Evaluation Kit
page. After downloading the software, it is recommended to use
the WinZip Extract function to extract all of the necessary
components as opposed to just clicking on setup.exe in the
zipped file. After extracting, click on seteup.exe in the folder
created during the extraction and follow the instructions on the
screen. If another version exists, it may be necessary to remove
as detailed in the above CD-ROM section.
USB Drivers
The software will also install the necessary USB drivers. After
installing the software, power up the CED board and connect to
the PC USB 2.0 port. The Windows “Found New Hardware
Wizard will display. Click on Next to install the drivers
automatically.
When installed properly, Windows displays the following.
On some PCs, the Found New hardware Wizard may show up
again and if so follow the same procedure to install it properly.
The “Device Manager” can be used to verify that the driver was
installed successfully.
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Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 5 of 26
Troubleshooting the Install
If the driver was not installed successfully the device manager
will display a question mark for Other devices as Windows
does not recognize the CED1Z board.
The “USB Device can be opened to view its uninstalled
properties.
This is usually the case if the software and drivers were installed
by a user without administrator privileges. If so, log on as an
administrator with full privileges and reinstall the software.
RUNNING THE EVALUATION SOFTWARE
The evaluation board includes software for analyzing the
AD7682, AD7689, AD7699 and AD7949. The EVAL-CED1Z is
required when using the software. The software is used to
perform the following tests:
Histogram for determining code transition noise (DC)
Fast Fourier transforms (FFT) for signal to noise ratio
(SNR), SNR and distortion (SINAD), total harmonic
distortion (THD) and spurious free dynamic range (SFDR)
Decimation (digital filtering)
The software is located at C:\Program Files\Analog Devices\
PulSAR ADC Evaluation Software\Eval PulSAR CED.exe.
A shortcut is also added to the Windows “Start” menu under
Analog Devices PulSAR ADC Evaluation Software”, “Eval
PulSAR CED. To run the software, select the program from
either location.
SETUP SCREEN
Figure 2 is the setup screen where ADC device selection, test
type, input voltage range, sample rate and number of samples
are selected.
CONFIGURING THE ADC
These ADCs need to be configured through a dedicated SPI
compatible serial port. The included SW configures the part to a
default configuration. Each of the different configurable
parameters are shown in the ADC Configuration section,
detailed in Figure 3 to Figure 7.
DC TESTING - HISTOGRAM
Figure 9 is the histogram screen, which tests the code
distribution for DC input and computes the mean and standard
deviation or transition noise. To perform a histogram test, select
“Histogram from the test selection window and click on the
“Start” radio button. Note: a histogram test can be performed
without an external source since the evaluation board has a
buffered VREF/2 source at the ADC input. To test other DC
values, apply a source to the J1/J2/P1-x inputs. It is advised to
filter the signal to make the DC source noise compatible with
that of the ADC.
AC TESTING
Figure 11 is the FFT screen, which performs an FFT on the
captured data and computes the SNR, SINAD, THD and SFDR.
Figure 12 is the time domain representation of the output. To
perform an AC test, apply a sinusoidal signal to the evaluation
board at the SMB inputs J1 for CH0 and J2 for CH1. Low
distortion, better than 100dB, is required to allow true
evaluation of the part. One possibility is to filter the input signal
from the AC source. There is no suggested bandpass filter but
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 6 of 26
consideration should be taken in the choice. Furthermore, if
using a low frequency bandpass filter when the full-scale input
range is more than a few Vpp, it is recommended to use the on
board amplifiers to amplify the signal, thus preventing the filter
from distorting the input signal.
Table 1. Jumper Description
Jumper Name Default
Position
Function
P5 - REFS Reference source selection.
REFS to middle pin: uses ADR435 (A1) 5V, 4.096V or 2.5V output.
VDD to middle pin: VDD supply is used as a reference.
Open: optional source can be connected to TP17/VREF.
P6 - BUF Reference buffer selection.
BUF to middle pin: buffer selection from P5 with the AD8032-A (U2).
NOBUFF to middle pin: use P5 direct (no buffer).
P7 REF/REFIN REF ADC REF/REFIN input selection.
REF to middle pin: external source drives ADC REF pin.
REFIN to middle pin: external source drives REFIN, reference buffer input pin
Open: When using the on-chip reference.
P8 COMS VCM Common channel select.
VCM to middle pin: for bipolar mode, selects VREF/2.
GND to middle pin: for unipolar operation, selects GND.
JP9 5V 5V External reference selection of 5V.
JP10 4.096V Open External reference selection of 4.096V.
JP11 2.5V Open External reference selection of 2.5V.
SB0-7 BUF Select BUF Use on-board analog amplifiers (U13 – U20)
BUF: use amplifier
NO BUF: bypass amplifier
- VDRV- -5V Amplifiers (U13-U20) (-) supply.
- VDRV+ 7V Amplifiers (U13-U20) (+) supply.
- VCCREF 12V ADR435(A1) (+) supply.
- VDDR 5V ADC (U7) VDD supply. Must always be the same as VDD.
- VDD 5V ADC (U7) VDD supply.
- VIO 3.3V ADC (U7) VIO interface supply.
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 7 of 26
Table 2.Test Points
Test
Point
Available
Signal
Type Description
TP8 GND P FPGA power supply GND.
TP9 -5VA1 P Amplifier negative supply.
TP10 +5VA1 P 5V analog supply.
TP11 +12VA1 P 12V analog supply.
TP12 GND P Analog supply GND.
TP13 VDD P ADC (U7) VDD supply.
TP14 VDDR P ADC (U7) VDD supply. Must always be = AVDD above.
TP15 VIO P ADC (U7) VIO interface supply.
TP17 VREF AI External reference input.
TP18 REF AI/O ADC on-chip reference output or external reference input.
TP19 REFIN AI/O ADC on-chip band-gap output or external reference input when using on-chip reference
buffer.
TP20 IN0 AI Analog input for ADC IN0 on both 4 and 8-channel ADCs.
TP21 IN1 AI Analog input for channel 1 on 8-channel ADCs only.
TP22 COM AI Sets the level on ADC COM; GND or VREF/2.
TP24 SDO DO Serial data output from ADC.
TP25 SCK DI Serial clock data input to ADC.
TP26 DIN DI Serial data input for part configuration.
TP27 CNV DI Conversion input to ADC
TP71 GND P Analog supply GND.
TP76 VDIG1 P FPGA power supply.
Table 3. Bill of Materials for the Connectors
Ref Des Connector Type Manf. Part No.
J1, J2, J3 RT Angle SMB Male Pasternack PE4177
P1 0.100 X 0.100 straight IDC header 2X10 3M 2540-6002UB
P2 0.100 X 0.100 straight IDC header 2X20 3M 2540-6002UB
P4 32X3 RT PC MOUNT CONNECTOR ERNI 533402
1 Supplied by EVAL-CED1Z when connected.
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EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 8 of 26
SOFTWARE OPERATION
Figure 2. Setup Screen
The following details the operation of the software.
1. The arrow is used to start the software. When running
is displayed.
2. The part to be evaluated is selected here.
3. The controls are used to set:
Sample Frequency units can be used such as 500k (case
sensitive) for 500,000 Hz.
Capture Mode – This selects between continuous (Cont.) or
burst conversion modes. In continuous mode, the ADC is
continuously converting. In Burst mode, the ADC is not
converting (sample clock held in inactive state) and the
conversions begin once the Single Capture” or Continuous
Capture buttons have been selected.
Interface mode – This selects the digital interface to the on-
board FPGA.
Input Range – this is used to adjust the LSB size in the data field
of the plot window.
4. These controls are used for saving, printing, help, etc. and are
also accessed in the File menu.
Save (F5): type – LabView config, allows the current
configuration to be saved to a filename.dat file. Useful when
changing many of the default controls. To load the saved
configuration, use the Load Previous Configuration. Note the
location of the .dat file. It is recommended to place into the
Support Files directory in the directory where the software was
installed.
Type – Html, saves the current screen shot to an Html file.
Type – Spreadsheet, saves the current data displayed in the chart
in a tab delimited spreadsheet. Raw ADC Data is time domain
in V or Code, FFT or Decimated is in dB.
5. Stop (F10) is used to stops the software. The can also be
used to stop the software. RESET is used to reset the EVAL-
CED1Z.
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Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 9 of 26
ADC CONFIGURATION
The ADC needs to be configured for input configuration,
reference, channel to be converted, temperature sensor, and on-
chip low pass (LP) filter (optional) for full bandwidth (BW) or
¼ BW. These next figures show the pull down configurations
available. Note the default value when the program is started is
indicated by the √; or CFG writing enabled, unipolar INn to
GND, CH0, full BW, and external reference. Note that after
updating the CFG, the first conversion (when using burst
mode) will be of the last configuration since the ADC has a 1-
depp delay for the CFG.
Figure 3 shows the default values.
Figure 3. Default CFG
Figure 4 details CFG Write Enabled/Disabled. When enabled,
the MSB of the CFG is set high. When disabled the MSB is set
low thus the remaining 13 bits are ignored.
Figure 4. CGF Enable/Disable Selection
Figure 5 details the inputs (IN0-IN7) configuration and channel
selection. Refer to the datasheet for more information about the
input configure-ations. Note that in the bipolar mode, the input,
IN+ and COM (or IN-) must be centered around VREF/2.
Figure 5. Input Configuration/Channel Selection
Figure 6 details the bandwidth selection of the 1-pole low pass
filter, which can reduce the noise from the amplifier circuit, if
desired. Note that the throughout of the converter must also
reduce to ¼ of the maximum when setting to ¼ BW.
Figure 6.BW Select
Figure 7 details the reference selection. Note that the TEMP
sensor can be used with an external reference. The Temp sensor
can be used to monitor the temperature of the ADC and the
output is straight binary and referenced to the ADC GND. The
displayed results should be in Volts format as opposed to Hex.
Figure 7. Reference Selection
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EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 10 of 26
Figure 8. Context Help, User Controls
1. To use the on-screen help. Select Help, Show Context Help or
click the Help (F1). An example of the Context Help is shown
above for the Sample Frequency. Placing the curser on most
screen items displays useful help for the particular control or
displayed unit.
2. These controls are used for axes and zooming panning.
Locks the graph axis to automatically fit the data.
Uses last axis set by user. , rescale the axes to the
automatic values.
, are used to set axes properties such as format,
precision, color, etc.
Displays the cursor.
Is used For zooming in and out.
Is used for panning.
Is used to set various graph properties such as graph
type, colors, lines, etc.
1
2
‘ mx ADL uMux 1mm i“: :m: szrzws mm“ new Raw Daxa Captur: Deumatmn .e Msamvksik11m ngnm Umlaszflve svemum Summa'v ‘ 4mm mun? ssnnr Sam: Fvequwi‘t annnr ‘ , 1 my mum mm mm , , E 1:; Camruaus u ZflDUV mam Mun: ' v 6 Made n. may mnnr cm; ('15:) fil'éfll cm ' gum my way “my and dim Emma. ”E men hm Range mm :e‘emd ma m We as; vlihge and mm 3278 32m made 0 . mummy) wad pm Caniguraoun ] Save (:5) I 1} I, {my He‘v (n: “3534] Damshuet mm 32%7 cm: (Isa) Histogram Dam Maxwme 1mm 3%; .5: "WWW.” 'W 1mm m :17“ us: a: thein hm Mn mama: am; V ms 1m; W 5 7 I53 w Wmd: m; A I I: ngurs 9. Hmogmm 5am L These radm bmmm are used m perflvrm a _ Ingle Caplur: or mm mm»: mm mm ’ “WM“ ’1 b (lununuuus Capture ufdala m m the : umeants mm. 'm m mum are displayed m the chm. Nute um um mum can be displayed as: mm ‘5 K 7 x mm ‘mnflhsmne‘spemum ‘swmuaw ” H / - msr a mm 2mm 3mm 4am ma mm mm mm m: Elm-lam: m Or an Oscilloscope 2‘, 3.1‘htsc d1 , , mm rtsptcuvcly. Rev PrD \ Page n we
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 11 of 26
Figure 9. Histogram Screen
1. These radio buttons are used to perform a Single Capture or
Continuous Capture of data set in the # of Samples field. The
results are displayed in the chart. Note that the results can be
displayed as:
A
Or an (time domain)
2., 3.These display the statistics for the X and Y-axes,
respectively.
1
2 3
m: 5 ‘ rm AIX‘ “MW Ipn vi may, Nam 23, 2am Raw Data Capture ngmm Summary ogram snnn , 4am , z. sonar U may w Deumatwun SummaN 'H'. ‘ nmuusmae Suemum 32755 32757 32755 32759 32770 , ursammes (k) 1) R Spectrum m, n, ,1“, 40, my W, ,1)” 71m: Kevmun 1.2 ANALOG DEVICES Pan 1' AD7SSS System com; um mm same Fremfini‘l 1 zsn Canmv: Millie" m mmmne mm a 1mm m‘nn sa‘nn «fun sa‘nu emu m‘nn an‘nn an‘nn m: nun m‘nn w‘uu sa‘nn su‘an mn‘m m‘m m‘m “We “557 Frenuancy am) 1mm Rang? Lg W‘s? ScoDEWzveform n 313 SumnlaryDaIz I - , i 'Fuvvawglawnganddam chmwmde km W [3 BE magnumwmnmbw V Ram: muxtbesekded ma ucufisgwman‘uww v "511755 .55 unmmVammmw. WEN) 9m; d3 nmom Name \ m gm 5. SNR (Sn/N) 711 55 as mmm‘wm yum dag -~—~-— THE 3 an Hmdamemal Remanzv m 122 m 1 m r—m v we M, m 55 JT w m: o g UmW‘ur/EWHV} maapyewuscunuguaom I Save(F5) I 1): LyEan q Heh (Fl) (“L334 Daushuet mm
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 12 of 26
Figure 10. Summary
The charts can be displayed together when the tab is selected.
‘ [val ADC uMux mlvi 5‘2 :an 0472mm wndn‘ nev “MQIJQLI mm, mm 25, zuna J s» w Raw Dam Captme ”Weflkmg _ Hfloqmm ‘Danasmve SDnCmm ‘Su'nrrsry J 4 Mm J J ANALOG DEVICES Part '1 AD7SS§ wwduw ; K352 J Sysiem Cmfiq Semis Fvequeni‘l g 1—‘2su m 5; Japan: :1: > a , , H Um; 5 mm Mm I‘lmx—ég‘Mo e n: max ' ‘oa-nam mm ‘ X mmange’ WWW My va—Sfii' mhmdqu) HEM I my “www.mmm mam um mam m‘m www-"WH‘W memmm an m: as; why: and mm Svectrum Dam Fvenuenry m ~ mndeb e Unw‘a/EWH} Max Amphmde )0 Mn mamas 17m 54? Pk“ Alum-1e ‘3s43x7 ' 7 H— H ‘—‘ Land P'evmuscunfiguvaom I acuweanrz‘a ' v mgr“ films“) 1), w 14w mJ—m . New“ any—mm m, um «mm m uw mm Riflfw‘ mum ms 11075 v 5m 5410455 m; ' 16“! amwmm [Fascia —“ mm D 'whcn the Spcdrum chart .5 : L Displays m: H- 2‘, 3. Diaplay the data for the x and Hm, rcspec
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 13 of 26
Figure 11. FFT Spectrum
1. Displays the FFT when the Spectrum chart is selected
2., 3. Display the data for the X and Y-axes, respectively.
3 2
1
1
‘ [val AIM. mm 1rfl-vi E12 :mx Ojeram flndw e‘v “mm! fill WWW _- ”DEVICES Hmwm Osu‘usmvfi ‘Snemum ‘Summary ‘ Part cam Made :1; (Wm 1., wapev glizhmg and am amahnm m: amen um \ Range mus‘besdsaed based an m: as? why: and mm . mndeb e Unw‘aI/Ew‘i} M“ W‘m 1am” v 2135;! 53 man Hevnuscanfiguaonn ] 5m (:5) I mmwmue home/M1730 15! Fundamemmewemwm km H ‘ (m £35“ 1 mum v £3,123? :53 my x , Enn'ig pm mm a: OffseWem ‘1 53175 , 1. 1m: dumam data
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 14 of 26
Figure 12 .Oscilloscope
1. Time domain data can be viewed with the oscilloscope also.
1
_ 7 n
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 15 of 26
EVALUATION BOARD SCHEMATICS AND ARTWORK
BOTTOM
BOTTOM
TOP
BOTTOM
BOTTOM
BOTTOM
1
7
<PTDE_ENGI NEER>
< PRODUCT _ 1>
AD7689/ 82/ 99/ 92
Topl evel
A
ad7689_csp_t opl evel
PAD
9
8
7
6
5
4
3
20
2
19
18
17
16
15
14
13
12
11
10
1
U7
1
TP7 4
1
TP71
C2
1
TP2
1
TP3
1
TP4
1
TP5
1
TP6
1
TP7
1
TP8
1
TP1
2
1
C1
2
1
C3
2
1
C4
2
1
C6
2
1
C5
0. 1UF
0. 1UF
10UF
BL KBL K
GND
0. 1UF
0. 1UF
BL K
BL KBL KBL K
BL K BL K
BL KBL K
TBD0805
DESI GNVIEW
ORFORANYOTHER PURPOSE DE TRI MENTALTOTHE I NTERESTS
D
THIS DRAWINGISTHEPROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ON S
OF
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S
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OWNEDOR C ONT ROL L EDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAY BE PROTECTEDBYPATENTS
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOGDEVICES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
96_pi n
AD<0. . 4 >
BD<0. . 1 5 >
BCS_ N
DSPCL K
CONTRO L
RESE T
BWR_ N
BRD_ N
BBUSY
+5VA
-12VA
+12VA
-5VA
GND
VDI G
GND
GND
GND
FPGA
V I O_ F P GA
EN_3. 3V_N
VFPGA
VPLLA2
VPLLA1
RESE T
CONTRO L
DSPCL K
BBUSY
BWR_ N
BRD_ N
BCS_ N
EN_7V_N
EN_5V_N
SCK
DI N
CNV
SDO
BD<0. . 1 5 >
VI O
AD<0. . 4 >
GND
ANALO G
REFI N
IN0/IN0
IN1
IN2/IN1
IN3
IN4
IN5/IN2
IN6
IN7/IN3
VDD
VDRV +
REF
COM
VCCRE F
VDRV -
POWER
VFPG A
VPLLA 2
VPLLA 1
VI O_FPG A
+12V A
+5VA
EN_3. 3 V_ N
EN_5V_ N
EN_7V_ N
VCCRE F
VDD
VI O
VDDR
VDRV -
VDRV +
-5VA
VDI G
Figure 13. Schematic, ADC + Block Diagram
u ‘ D (r a a g L L _ k i ‘ W .‘ z I" g _(_‘ 7 , 1;: i g é g ~ J 4 X m p n )7 a 4 o A (r 4 .L A, .2. :‘i 5‘ 3‘ i a 'g‘: ' m E a m f a H 4 . i g g‘ g E z , r x 2' 9 7 m r g a 7. m 1 2 5 h” a a § “L .u 7' 2 m n U ' H 3% U :3; ”x 5:: 3i: 5; six “L J K ~ e—R> H; e—O—b / a a: {3 I ’I 9 b—ib 40—;9 J.) ; A 7 j 2:“ as :20 7 i ists'j’u.n;f 31.3"”: 9:79.": 03$: "“ :55 g 3 5D i a ‘ 5 ‘ ~ ,. I m M .J \ a c
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 16 of 26
VI O
+12VA+5VAGND-5VA
EXT
VDD
VDDR
LDO ADJUSTED TO 1. 2V
L DO A DJ US TE D T O 1 . 2 V
LDO ADJUSTED TO 1. 2V
REGULATE S FPGA VI O SUPPLI ES TO 3. 3V ( MAX AL L OWED)
ANALOG SUPPLI ES
FPGA SUPPLI ES
SUPPLY OPTI ONS
2
7
<PTDE_ENGI NEER>
< PRODUCT _ 1>
AD7689/ 82/ 99/ 92
Topl evel
A
powe r
2
1
P9
C7
6
PAD
2
1
8
7
5
3
U8
R5 6
C8
R5 5
C9
1
TP39
1
TP38
1
TP40
1
TP42
1
TP41
1
TP43
1
TP46
1
TP45
1
TP44
1
TP47
1
TP36
1
TP35
1
TP37
1
TP33
1
TP34
1
TP32
1
TP31
1
TP30
1
TP29
1
TP28
1
TP7 6
1
TP1 6
1
TP1 1
1
TP1 2
1
TP9
1
TP1 0
1
TP1 5
1
TP1 4
1
TP1 3
C1 4
C1 5
C1 6
C1 3
C1 2
C1 1
6
PAD
2
1
8
7
5
3
U1 2
C3 4
C2 8 C2 7
C3 3 C3 2
C2 6
2
1
C1 7
2
1
R2
3
2
8
7
65
1
4
U9
2
1
R1
2
1
C20
2
1
C23
2
1
R7
2
1
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2
1
R9
2
1
R1 9
2
1
R2 1
2
1
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2
1
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2
1
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2
1
R1 0
2
1
C2 1
2
1
C1 8
2
1
C1 9
2
1
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2
1
R1 8
2
1
R1 7
2
1
R14
2
1
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2
1
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3
2
8
7
65
1
4
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2
1
R5
2
1
R4
3
2
8
7
65
1
4
U1 0
2
1
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2
1
C2 5
2
1
C2 4
2
1
C2 9
2
1
R1 3
6
PAD
2
1
8
7
5
3
U4
2
1
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2
1
R15
6
PAD
2
1
8
7
5
3
U3
2
1
C3 0
RED
BL U
+5V
+12VA
VCCREF
GND
VDRV-
+5V
+7V
VDRV+
+12VA
10UF
REDRED
RED
RED
RED
RED
10UF
REDREDRED
10UF
2. 2UF
0. 1UF
2. 2UF
78. 7K
1000PF
140K
VDI G
VDI G
VDI G
VDI G
RED
2. 2UF
ADP333 4ACPZ
V I O_ F PGA
VPLLA2
VPLLA1
VFPGA
VCCREF
VDDR
VDD
VI O
VDRV-
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EN_7V_N
EN_5V_N
EN_3. 3V_N
VDI G
-5VA
+5VA
+12VA
AV21+AV5+AV5-TXE
VI O
VDDR
VDD
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BL K
RED
RE D
REDREDRED
DERDER
RED RED
RED
RED
10UF
10UF
10UF
BL U
2K
2. 2UF
1K
0
0. 1UF
2. 2UF
1K
2K
1K
ADP171 5ARMZ- R7
0
2. 2UF
0. 1UF
0
V I O_ F PGA
+7V
+5V
V I O_ F PGA
+3. 3V
EN_7V_N
EN_5V_N
+12VA
+12VA
EN_3. 3V_N
+5VA
10K
10K
2. 2UF
ADP3334ACPZ
60. 4K
1000PF
300K
2. 2UF
ADP3334ACPZ
64. 9K
1000PF
210K
2. 2UF
0
0
10K
2. 2UF
ADP333 4ACPZ
78. 7K
1000PF
140K
2. 2UF
0
VI O_ FPGA
V I O_ F PGA
VPLLA2
ADP171 5ARMZ- R7
ADP1715ARMZ- R7
2. 2UF
2. 2UF
2K
VPLLA1
VFPGA
2. 2UF
BL U
+7V
-5VA
+5V
+5V
EXT
EXT
EXT
+3. 3V
RED
DESI GNVIEW
ORFORANYOTHER PURPOSE DETRI MENTALTOTHE I NTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ON S
OF
O
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G
S
E
OWNEDOR C ONT ROL L EDBYOWNEDANALOGDEVICES.
THEEQUIPMENTSHOWNHEREONMAY BE PROTECTED BY PATENTS
INPART,ORUSEDINFURNISHINGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOGDEVICES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
GND
GND
OUT
GND
IN1
IN2
OUT 2
OUT1
PAD FB
GND
SD*
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN1
IN2
OUT 2
OUT1
PAD FB
GND
SD*
OUT
IN1
IN2
OUT 2
OUT1
PAD FB
GND
SD*
GND
GND
GND
IN1
IN2
OUT 2
OUT1
PAD FB
GND
SD*
GND
GND
GND
OUT
ADJ GND
EN
IN
OUT
GND
GND
GND
GND
OUT
OUT GND
GND
OUT
ADJ GND
EN
IN
OUT
ADJ GND
EN
IN
OUT
Figure 14. Schematic, Supplies
. 7 m a 7 r a 7 I , E n_ 2‘. 7n: 7 émanu 2:57 on 25.5 a 3K 7 “Ha; m 1 h 0‘ 7:: . 41 4v: n21.) 95313 J/o‘in \Jvaj 47 414233 1i! .7 7 7 7 531 i 7 .25: 7.» . ‘ :7‘ n m V 7 m m p o
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 17 of 26
4. 096V
REF S
VREF
VDD
VREF
2. 5V
REF
REF
5V
BI ASI NG USI NG ADC REF
REF I N
REF I N
BUF
NOBUF
EXTERNAL REFERENCE OPTI ONS
3
7
<PTDE_ENGI NEER>
<PRODUCT_1>
AD7689/ 82/ 99/ 92
Topl evel
A
anal og
2
1
JP9
C3 7
C4 0
C4 2
1
3
2
U1
2
1
JP11
2
1
JP10
C3 5
C3 8
C4 5
C4 3
C4 1
1
TP1 9
1
TP1 7
1
TP1 8
R2 2
4
8
U2
1
3
2
U2
R3 0
R3 2
R2 9
R2 8
R2 6
2
1
R2 7
2
1
C3 6
6
2
5
8
1
7
3
4
A1
2
1
R2 3
2
1
R2 4
2
1
R2 5
3
2
1
P5
2
1
C3 9
3
2
1
P6
3
2
1
P7
7
5
6
U2
4
8
U1
2
1
C4 4
2
1
R3 1
2
1
R3 3
7
5
6
U1
VCCREF
TBD0805
1K
AD8032ARZ
0. 1UF
10K
REFI N
VDD
2. 2UF
REF I N
REF
VCCREF
10K
TBD0805
0
10UF
0. 1UF
ADR4 3 5 BRZ
45. 3K
1K
AD8032ARZ
1K
YEL
BL U
AD8032ARZ
AD8032ARZ
AD8032ARZ
AD8032ARZ
VCCREF
VBI AS
VCM
REF
VDD
10K
10K
10K
10K
0. 1UF
10UF
10UF
10UF 10UF
10UF
BL U
VCCREF
DESI GNVIEW
ORFORANYOTHER P URPOSE DETRI MENTALTOTHE I NTERESTS
D
THIS DRAWINGISTHEPROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
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RE V
DATE APPROVED
B
6
DESCRI PTI ON
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OF
O
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OWNEDORCONTROLLEDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWN HEREONMAY BE PROT ECTEDBYPATENTS
IN PART,ORUSED I N FURNI S HI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOGDEVICES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
V-
V+
GND
GND
GND
OUT
OUT
GND
TRI M
VI N
GND
NC1
TP
NC2
TP1
VOUT
GND
GND
V-
V+
GND GND GND
GND GND
Figure 15. Schematic, Reference, Buffer, VCM, VBIAS
”I , d in
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 18 of 26
IN0/IN0
IN1
ADC BUFFERS
4
7
<PTDE_ENGI NEER>
< PRODUCT _ 1>
AD7689/ 82/ 99/ 92
Topl evel
A
anal og
54
3
2
1
J3
R4 9R3 5
1
TP52
1
TP53
1
TP51
1
TP49
1
TP50
1
TP48
1
TP58
1
TP59
1
TP57
1
TP56
1
TP55
1
TP54
R1 5 7 R1 5 6
9
8
7
6
5
4
3
2
16
15
14
13
12
11
10
1
P1
C4 7
R4 3
R4 5
C4 9
1
TP21
1
TP2 0
2
1
C6 2
2
1
R6 4
2
1
R6 6
2
1
C6 4
2
1
C6 1
2
1
R6 0
2
1
R6 5
2
1
C6 3
C6 9
C6 8
C6 7
C7 2
C71
C7 0
C5 7
C5 6
C5 5
C5 2
C5 4
C5 3
54
3
2
1
J2
54
3
2
1
J1
2
1
R4 2
2
1
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2
1
R4 7
4
7
8
6
3
5
1
2
U1 4
2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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4
7
8
6
3
5
1
2
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
1
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2
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1
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1
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4
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2
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2
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IN5/IN2
CH7 / CH3
CH5 / CH2
CH2 / CH1
CH0 / CH0
IN2/IN1
IN3
CH0 / CH0
CH2 / CH1
CH3
IN7/IN3
IN6
IN4
IN3
IN2/IN1
IN1
IN0/IN0
CH6
CH4
CH3
CH1
CH1
IN1
IN0/IN0
BL U
10K
0. 1UF
TBD0805TBD0805
TBD0805TBD0805
TBD0805TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
RED
ADA4841- 1YRZ
TBD0805
0
TBD0805
0. 1UF
49. 9
TBD0805
0. 1UF
0
VDRV+
VDRV-
VDRV-
EXT_ COM
0
TBD0805
TBD0805
TBD0805 TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
22
RED
RED
RED
ADA4841- 1YRZ
ADA4841- 1YRZ
RED
RED
RED
22
2700PF
RED
RED
RED
22
2700PF
10K
2700PF
BL U
RED
RED
22
2700PF
49. 9 49. 9
49. 9
0
0
0
0
0
00
0
0
VBI AS
VDRV-
VDRV+
COM
VDRV-
VDRV-
VDRV+
ADA4841- 1YRZ
VDRV+
VDRV+
590 590
590
0. 1UF
0. 1UF
0. 1UF
0. 1UF
0. 1UF
0. 1UF
0. 1UF
VBI AS
0. 1UF
VBI AS
0. 1UF
590
VBI AS
0
DESI GNVIEW
ORFORANYOTHER PURPOSE DETRI MENTALTOTHE I NTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ON S
OF
O
L
G
S
E
OWNEDORCONTROLLEDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAYBEPROTECTED BY PATENTS
INPART,ORUSED I N FURNI SHI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOGDEVICES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
PD_N
N2
N1
V-
V+
GND
PD_N
N2
N1
V-
V+
GND
GND
GND
GND
GND
GND
PD_N
N2
N1
V-
V+
GND
GND
GND
GND GND
GNDGND
GND
PD_N
N2
N1
V-
V+
GNDGND GND
GND GND GND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
GND
GND
GND
Figure 16. Schematic, AnalogCH0-CH3
57:78 rELW arr
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 19 of 26
ADC BUFFERS CONTI NUED
COM
5
7
<PTDE_ENGI NEER>
< PRODUCT _ 1>
AD7689/ 82/ 99/ 92
Topl evel
A
anal og
1
TP78
1
TP77
1
TP79
1
TP70
1
TP69
1
TP72
1
TP61
1
TP60
1
TP62
1
TP67
1
TP66
1
TP68
1
TP64
1
TP63
1
TP65
C91
R9 9
1
TP2 2
2
1
C9 2
2
1
R1 0 5
2
1
R1 1 0
2
1
C9 4
C1 0 0
C9 9
C9 8
2
1
C9 3
2
1
R1 0 9
2
1
R1 1 1
2
1
C9 5
C1 0 3
C1 0 2
C1 0 1
2
1
C7 7
2
1
R8 5
2
1
R8 7
2
1
C7 9
C8 7
C8 6
C8 5
2
1
C7 6
2
1
R8 1
2
1
R86
2
1
C7 8
C8 4
C8 3
C8 2
2
1
R8 3
2
1
R8 4
2
1
R8 9
4
7
8
6
3
5
1
2
U1 8
2
1
R8 2
2
1
R9 2
2
1
C8 1
2
1
R9 4
2
1
R9 8
2
1
C8 9
2
1
R1 0 8
2
1
R1 0 7
2
1
R1 0 6
2
1
R7 9
2
1
R8 0
2
1
R7 8
2
1
R8 8
4
7
8
6
3
5
1
2
U1 7
2
1
R9 0
2
1
C8 0
2
1
R9 3
2
1
R9 7
2
1
C8 8
2
1
R1 0 4
2
1
R1 0 3
2
1
R1 0 2
2
1
R1 1 3
4
7
8
6
3
5
1
2
U2 0
2
1
R1 1 8
2
1
R1 1 6
2
1
C9 7
2
1
R1 2 0
2
1
C1 0 5
2
1
R1 1 2
4
7
8
6
3
5
1
2
U1 9
2
1
R1 1 7
2
1
R1 1 4
2
1
C9 6
2
1
R1 1 9
2
1
C1 0 4
3
2
1
P8
0
TBD0805
0. 1UF
TBD0805
CH6
IN6
IN7/IN3
CH5 / CH2
IN5/IN2
CH7 / CH3
IN4
CH4
TBD0805
TBD0805
TBD0805 TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
RED
ADA4841- 1YRZ
0. 1UF
0
ADA4841- 1YRZ
0. 1UF
22
RED
VBI AS
0. 1UF
ADA4841- 1YRZ
RED
RED
RED
VCM
22
VDRV-
0. 1UF
VDRV+
0. 1UF
49. 9
VBI AS
0. 1UF
0. 1UF
0. 1UF
VBI AS
0. 1UF
0. 1UF
VBI AS
0. 1UF
49. 9 49. 9
VDRV- VDRV-
VDRV-
VDRV+VDRV+
VDRV+
0
0
0
0
0
0
0
0
0
0
590
590 590
590
2700PF
49. 9
2700PF
22
RED
22
RED
RED
RED
2700PF
22
RED
RED
RED
2700PF
ADA4841- 1YRZ
2700PF
BL U
RED
RED
RED
EXT_ COM
COM
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805
TBD0805TBD0805
TBD0805
TBD0805
TBD0805
DESI GNVIEW
ORFORANYOTHER PURPOSE DE TRI MENTALTOTHEINTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ON S
OF
O
L
G
S
E
OWNEDOR C ONT ROL L EDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAY BE PROTECTED BY PATENTS
INPART,ORUSED I N FURNI SHI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOG DEVI CES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
GND
GND
GND
GND GND
GND
GND GND
GND
GND GND
GND
GND GND
GNDGND
PD_N
N2
N1
V-
V+
GND
GND
PD_N
N2
N1
V-
V+
GND
GND
PD_N
N2
N1
V-
V+
GND
PD_N
N2
N1
V-
V+
GND
Figure 17. Schematic, AnalogCH4-CH7
E L "i xmngsm g( g i ”l -]
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 20 of 26
BANK_2
ADCOK
MCL K
DUT_ I / O
96_PI N_I / O
BANK_3
BANK_4
BANK_1
SUPPLI ES
POWER_FPGA
6
7
<PTDE_ENGI NEER>
< PRODUCT _ 1>
AD7689/ 82/ 99/ 92
Topl evel
A
fpga
2
1
P10
2
1
P11
R125
1
TP7 3
9
8
7
6
5
40
4
39
38
37
36
35
34
33
32
31
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
P3
1
TP2 7
1
TP2 6
1
TP2 5
1
TP2 4
C128
C130
C131
C1 2 7
C1 2 9
C1 0 9 C110
R126
C125
C126
C122
C124
C118
C120
C115
C116
C113
C111
C1 0 8
R1 2 3
R132
R130 R1 2 8
C1 0 7
R1 2 4
C1 1 2 C1 1 4 C1 1 7 C1 1 9
C1 2 1
C1 2 3
2
1
R13 6
2
1
R1 5 0
2
1
R13 7
2
1
R1 5 1
2
1
R1 4 4
2
1
R1 4 3
2
1
R1 4 2
2
1
R1 4 1
2
1
R1 4 0
2
1
R1 3 9
2
1
R1 3 8
2
1
R1 3 4
2
1
R1 2 2
2
1
R1 2 1
2
1
R1 3 5
2
1
R1 4 5
AC
CR1
9
8
7
6
5
4
3
2
10
1
P2
8
7
3
1
4
62
5
U5
4
3
2
1
Y3
T15
T2
P10
P7
M1 0
M7
R1 6
K14
G1 4
B16
E10
E7
C1 0
C7
A15
A2
R1
K3
G3
B1
J7
H1 0
H7
G9
C8
B15
B2
A16
A1
J8
H9
K9
J9
T16
T1
R1 5
R2
P9
H8
P8
M9
M8
J14
J3
H1 4
H3
E9
E8
C9
G8
U6
L6
G1
G2
H5
F2
J5
G5
D3
E4
E3
E5
D5
C2
M4
L4
C1
P3
P2
P1
L3
N2
N1
M3
M2
J4
L2
F4
L1
M1
K5
K4
K1
K2
E2
E1
F3
D4
C3
N5 L5
H4
F1
J1
J2
H1
H2
U6
E12
F6
E6
B3
A3
A4
B4
A5
B5
C4
C5
C6
D6
G7
G6
A6
B6
D8
F8
F7
B7
A7
A8
B9
A9
D1 0
D1 1
F9
F10
A10
B10
G1 1
G1 0
C1 1
A11
A12
B12
B11
A13
B13
C1 2
C1 3
A14
B14
E11
U6
F11
M1 3
K1 2
J13
G1 3
G1 2
H1 1
J11
F16
F15
G1 5
G1 6
J12
H1 2
K1 5
K1 6
L16
L15
L14
M1 4
M1 6
M1 5
N1 6
N1 5
P1 6
P1 5
P1 4
N1 4
N1 3
M1 2
N1 2
D1 4
E1 4
D1 3
C1 4
E1 6
D1 6
D1 5
H1 3
D1 2
F1 2
L13
J16
J15
H1 5
H1 6
U6
M5
L11
M1 1
R1 4
T14
R1 3
T13
L12
R1 2
T12
P13
P12
N1 1
K10
K11
T10
R1 0
L10
L9
P11
R1 1
T11
N1 0
N9
R9
T9
R8
T8
L8
L7
R7
T7
N8
T6
R5
T5
R4
T4
P4
P5
T3
R3
M6
U6
VFPGA
VCCI O1
V I O_ F P GA
VI O
V I O_ F PGA
EP2C5F256C7N
VFPGA
VI O_ FPGA
EP2C5F256C7N
EN_5V_N
EN_3. 3V_N
BCS_N
AD<2>
SCK
EN_7V_N
18
5
60. 4
ADCOK
DSPCL K
RESET
BBUSY
10K
10K
BD<7>
VCCI O1
.1UF
ASDO
PS_STATUS_N
PS_ CONF I G_ N
ASDO
EPCS4SI 8N
ASDO
1000PF
V I O_ F PGA
V I O_ F PGA
V I O_ F PGA
V I O_ F P GA
V I O_ F PGA
VI O_ FPGA
VI O_ FPGA
V I O_ F PGA
V I O_ F P GA
PS _ CONF I G_ N
PS_STATUS_N
100MH Z
DAT A
10K
DAT A
N_ CSO
DI N
1000PF
VPLLA2
LA_D<0. . 31>
BD<0. . 15>
MCL K
BL U
15K
10K
CNV
BCS_N
CONTROL
BBUSY
BBUSY
10K
VI O
PS _ CDONE _ N
BD<6>
BD<5>
BD<3>
BD<14>
AD<3>
AD<4>
BWR_ N
BD<11>
BD<9>
VFPGA
MS E L 1
MS E L 0
DSP CL K
ADCOK
BRD_ N
RESET
AD<1>
AD<0>
BD<15>
BD<13>
BD<12>
BD<10>
BD<8>
BD<4>
BD<2>
BD<1>
BD<0>
PS _ CDONE _ N
EP2C5F256C7N
EN_7V_N
LA_D<0. . 31>
VPLLA1
7
SDO
10K
VPLLA1
10K
PS _ DCL K
0
PS_DCLK
N_ CSO
N_ CSO
MCL K
PS_DCLK
CONTROL
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF
.1UF .1UF .1UF .1UF .1UF
0
0
10K
10K
BWR_ N
10K
BRD_ N
10K
10K
10K
10K
BL U
EP 2C5 F 2 5 6C7 N
EP 2C5 F 2 5 6C7 N
LA_CLK2LA_CLK1
LA_CLK2
16
12
25
BWR_ N
CONTROL
DSPCL K
20
21
MSEL0
30
29
28
27
26
25
24
23
22
19
18
17
16
15
14
13
12
11
10
9
8
6
5
4
3
2
1
0
MSEL1
VI O
GND
31
30
29
28
24
23
22
21
20
19
17
15
14
13
11
10
9
8
7
6
4
3
2
1
0
EN_5V_N
SDO
BCS_N
BRD_ N
RESET
DI N
CNV
3M2510- 5002UB
GND
GND
AD<0..4>
26
27
31
LA_CLK1
.1UF
VFPGA
SCK
BL U
BL U
VFPGA
TBD0603
EN_3. 3V_N
10K
15K
VPLLA2
V I O_ F PGA
DAT A
YEL
DESI GNVIEW
ORFORANYOTHER PURPOSE DETRI MENTALTOTHE I NTERESTS
D
THIS DRAWINGISTHE PROPERTYOFANALOGDEVICESINC.
SCALE
D
D
D
SI ZE
D
REV
SHEET
1
2
1
A
2
3
4
3
5
8
D
7
6
7
8
A
B
CC
D
5
4
RE V
DATE APPROVED
B
6
DESCRI PTI ON
REVI SI ON S
OF
O
L
G
S
E
OWNEDORCONTROLLEDBYOWNEDANALOG DEVI CES.
THEEQUIPMENTSHOWNHEREONMAYBEPROTECTED BY PATENTS
INPART,ORUSED I N FURNI SHI NGINFORMATIONTOOTHERS,
IT IS NOT TO BE REPRODUCEDORCOPIED,INWHOLEOR
E
A
N
A
VC
OFANALOGDEVICES.
PTDE ENGI NEER
DRAWING NO.
SCHEMATI C
VCCI O4VCCI O3VCCI O2VCCI O1VCCI NT
GND
VCCD_ P L L1
TDO
TMS
TDI
TCK
NCONFI G
NCE
DCLK
DATA0
CL K3
CL K2
CL K1
CL K0
GND_ PL L1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
GND
GND
GND
GND
IN
GND
GND
GND
GND
VCCA_PLL2
GNDA_PLL2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
ASDI
DCLK
VCC
DATA
nCS
GND
GND
GND
GND
V+
GND
OUT
EN
GND
GND
GND
GND
VCCD_ P L L 2
MSEL1
MSEL0
CLK7
CLK6
CLK5
CLK4
GND_ PL L2
NSTATUS
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
CONF_ DONE
VCCA_PLL1
GNDA_PLL1
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Figure 18. Schematic, FPGA
. anus r175» nu: 7 u 7 , n m u 7
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 21 of 26
BD<15>
AD<0>
AD<3>
AD<4>
VDI G
-5VA
+5VA
- 12VA
+12VA
DSPCL K
CONTROL
RESET
BWR_ N
BRD_ N
BBUSY
BCS_N
AD<1>
BD<13>
BD<11>
BD<12>
BD<10>
BD<9>
BD<8>
BD<0. . 15>
BD<3>
BD<2>
4
3
1
0
15
14
13
11
12
9
8
7
6
5
4
3
2
1
0
GND
GND
BD<14>
BD<0>
BD<1>
BD<4>
BD<6>
10
ERNI 533402
VDI G
BWR_ N
BCS_N
AD<4>
BBUSY
BD<14>
BD<15>
+12VA
-5VA
+5VA
CONTROL
BD<0 >
BD<1 >
BD<2 >
BD<3 >
BD<4 >
VDI G
BD<7 >
BD<8 >
BD<13>
-5VA
+5VA
VDI G
AD<3>
RESET
BD<12>
DSPCL K
- 12VA
-5VA
+5VA
AD<0..4>
BD<5>
GND
BD<5 >
BD<6 >
BD<11>
BRD_ N
BD<10>
AD<2>
AD<0>
BD<9 >AD<1>
ERNI 533402ERNI 533402
BD<7>
GND
AD<2>
2
96_pin
A
Topl evel
AD7689/ 82/ 99/ 92
< PRODUCT _ 1>
<PTDE_ENGI NEER>
77
P4
C1
C1 0
C1 1
C1 2
C1 3
C1 4
C1 5
C1 6
C1 7
C1 8
C1 9
C2
C2 0
C2 1
C2 2
C2 3
C2 4
C2 5
C2 6
C2 7
C2 8
C2 9
C3
C3 0
C3 1
C3 2
C4
C5
C6
C7
C8
C9
P4
B1
B1 0
B11
B1 2
B1 3
B1 4
B1 5
B1 6
B1 7
B1 8
B1 9
B2
B2 0
B21
B2 2
B2 3
B2 4
B2 5
B2 6
B2 7
B2 8
B2 9
B3
B3 0
B31
B3 2
B4
B5
B6
B7
B8
B9
P4
A1
A1 0
A11
A1 2
A1 3
A1 4
A1 5
A1 6
A1 7
A1 8
A1 9
A2
A2 0
A21
A2 2
A2 3
A2 4
A2 5
A2 6
A2 7
A2 8
A2 9
A3
A3 0
A31
A3 2
A4
A5
A6
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Figure 19. Schematic, 96-Pin Interface
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 22 of 26
Figure 20. Top Side Silk-Screen
(Viewed from top side)
Figure 21. Inner Layer 1
(Viewed from top side)
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 23 of 26
Figure 22. Ground Plane
(Viewed from top side)
Figure 23. Inner Layer 2
(Viewed from top side)
.Ilr ‘Ilr 'llr 'III' ‘Ilr ‘Ilr ‘Ilr 1-» A... r... A ':'3 ' p.15 jail/Eié—fi:
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 24 of 26
Figure 24.Inner Layer 3
(Viewed from top side)
Figure 25. Bottom Layer
(Viewed from top side)
Preliminary Technical Data EVAL-AD76MUXEDZ
Rev. PrD | Page 25 of 26
Figure 26. Bottom Layer
(Viewed from Bottom Side)
ANALOG DEVICES www.analng.cnm
EVAL-AD76MUXEDZ Preliminary Technical Data
Rev. PrD | Page 26 of 26
ORDERING GUIDE
Evaluation Board Model Product
EVAL-AD7682EDZ AD7682BCPZ
EVAL-AD7689EDZ AD7689BCPZ
EVAL-AD7699EDZ AD7699BCPZ
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EVAL-CED1Z Capture/Controller Board
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