ADC1207S080 Datasheet by NXP USA Inc.

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1. General description
The ADC1207S080 is a 12-bit Analog-to-Digital Converter (ADC) optimized for direct
Input Frequency (IF) sampling and supporting the most demanding use conditions in ultra
high IF radio transceivers for cellular infrastructure and other applications such as wireless
infrastructure, optical networking and fixed telecommunication. Due to its broadband input
capabilities, the ADC1207S080 is ideal for single and multiple carriers data conversion.
Operating at a maximum sampling rate of 80 MHz, analog input signals are converted into
12-bit binary coded digital words. All static digital inputs are CMOS compatible. All output
signals are Low-Voltage Complementary Metal-Oxide Semiconductor (LVCMOS)
compatible. The ADC1207S080 offers the most flexible acquisition control system
because of its programmable Complete Conversion Signal (CCS) that allows to adjust the
delay of the acquisition clock.
The ADC1207S080 offers the lowest input capacitance (< 1 pF) and therefore the highest
flexibility in front-end aliasing filter strategy because of its internal front-end buffer.
2. Features
n12-bit resolution
nDifferential input with 375 MHz bandwidth
n90 dB SFDR; 71 dB S/N (fi= 225 MHz; fclk = 80 MHz; B = 5 MHz)
n74 dB SFDR; 66.5 dB S/N (fi= 175 MHz; fclk = 80 MHz; B = Nyquist)
nHigh speed sampling rate up to 80 MHz
nInternal front-end buffer (input capacitance < 1 pF)
nProgrammable acquisition output clock (complete conversion signal)
nFull-scale controllable from 1.5 V to 2 V (p-p); continuous scale
nSingle 5 V power supply
n3.3 V LVCMOS compatible digital outputs
nBinary or two’s-complement LVCMOS outputs
nCMOS compatible static digital inputs
nOnly 2 clock cycles latency
nIndustrial temperature range from 40 °C to +85 °C
nHTQFP48 package
ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF
sampling
Rev. 02 — 7 August 2008 Product data sheet
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 2 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
3. Applications
High speed analog to digital conversion for:
nRadio transceivers
nWireless infrastructure
nCable modem
nDigital storage scope
nFixed telecommunication,
nOptical networking
nWireless Local Area Network (WLAN) infrastructure.
nGeneral purpose applications
4. Ordering information
5. Block diagram
Table 1. Ordering information
Type number Package Sampling
frequency
(MHz)
Name Description Version
ADC1207S080HW HTQFP48 plastic thermal enhanced thin quad flat package; 48 leads;
body 7 ×7×1 mm; exposed die pad SOT545-2 80
Fig 1. Block diagram
1212
2
014aaa430
TRACK
AND
HOLD
ADC
CORE
LATCH
LATCH
RESISTOR
LADDERS
CLOCK DRIVER
OUTPUTS
ENABLE
CMADC
REFERENCE
VREF
REFERENCE
ADC1207S080
U/I
front-end
buffer
FSOUT
INN
FSIN
IN
DEL0 to
DEL1
CCS
D0 to D11
OTC
VCCO
IR
DECCMADC
CLK CLKN
CE_N
pe
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 3 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 2. Pin configuration
ADC1207S080HW
n.c. D0
AGND1 D1
IN D2
CMADC D3
INN D4
AGND1 D5
DEC D6
n.c. D7
FSOUT D8
FSIN D9
n.c. D10
n.c. D11
DGND
n.c. AGND1
DEL1 VCCA1
DEL0 AGND1
VCCD2 VCCA1
DGND2 VCCA2
CE_N AGND2
OTC DGND1
OGND VCCD1
VCCO CLK
OGND CLKN
VCCO
IR
DGND1
CCS
014aaa431
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
48
47
46
45
44
43
42
41
40
39
38
37
24
Table 2. Pin description
Symbol Pin Type[1] Description
n.c. 1 - not connected
AGND1 2 G analog ground 1
IN 3 I analog input voltage
CMADC 4 O regulator common mode ADC output
INN 5 I complementary analog input voltage
AGND1 6 G analog ground 1
DEC 7 I/O decoupling node
n.c. 8 - not connected
FSOUT 9 O full-scale reference voltage output
FSIN 10 I full-scale reference voltage input
n.c. 11 - not connected
n.c. 12 - not connected
n.c. 13 - not connected
DEL1 14 I complete conversion signal delay input 1
DEL0 15 I complete conversion signal delay input 0
VCCD2 16 P digital supply voltage 2 (5.0 V)
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 4 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
[1] P: power supply; G: ground; I: input; O: output.
DGND2 17 G digital ground 2
CE_N 18 I chip enable input (CMOS level; active LOW)
OTC 19 I control input for two’s complement output (active HIGH)
OGND 20 G data output ground
VCCO 21 P data output supply voltage (3.3 V)
OGND 22 G data output ground
VCCO 23 P data output supply voltage (3.3 V)
IR 24 O in-range output
D11 25 O data output bit 11 (Most Significant Bit (MSB))
D10 26 O data output bit 10
D9 27 O data output bit 9
D8 28 O data output bit 8
D7 29 O data output bit 7
D6 30 O data output bit 6
D5 31 O data output bit 5
D4 32 O data output bit 4
D3 33 O data output bit 3
D2 34 O data output bit 2
D1 35 O data output bit 1
D0 36 O data output bit 0 (Least Significant Bit (LSB))
CCS 37 O complete conversion signal output
DGND1 38 G digital ground 1
CLKN 39 I complementary clock input
CLK 40 I clock input
VCCD1 41 P digital supply voltage 1 (5.0 V)
DGND1 42 G digital ground 1
AGND2 43 G analog ground 2
VCCA2 44 P analog supply voltage 2 (5.0 V)
VCCA1 45 P analog supply voltage 1 (5.0 V)
AGND1 46 G analog ground 1
VCCA1 47 P analog supply voltage 1 (5.0 V)
AGND1 48 G analog ground 1
DGND exposed
die pad G digital ground
Table 2. Pin description
…continued
Symbol Pin Type[1] Description
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 5 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
7. Limiting values
[1] The supply voltages VCCA and VCCD may have any value between 0.5 V and +7.0 V provided that the
supply voltage differences VCC are respected.
[2] The supply voltage VCCO may have any value between 0.5 V and +5.0 V provided that the supply voltage
differences VCC are respected.
8. Thermal characteristics
[1] In compliance with JEDEC test board, in free air.
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCCA analog supply voltage [1] 0.5 +7.0 V
VCCD digital supply voltage [1] 0.5 +7.0 V
VCCO output supply voltage [2] 0.5 +5.0 V
VCC supply voltage difference VCCA VCCD 1.0 +1.0 V
VCCD VCCO 1.0 +4.0 V
VCCA VCCO 1.0 +4.0 V
Vi(IN) input voltage on pin IN referenced to AGND 0 VCCA +1 V
Vi(INN) input voltage on pin INN referenced to AGND 0 VCCA +1 V
Vi(CLK) input voltage on pin CLK referenced to DGND 0 VCCD +1 V
Vi(CLKN) input voltage on pin CLKN referenced to DGND 0 VCCD +1 V
IOoutput current - 10 mA
Tstg storage temperature 55 +150 °C
Tamb ambient temperature 40 +85 °C
Tjjunction temperature - 150 °C
Table 4. Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient [1] 36.2 K/W
Rth(j-c) thermal resistance from junction to case [1] 14.3 K/W
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 6 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
9. Characteristics
Table 5. Characteristics
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
40
°
C
to +85
°
C; V
i(IN)
V
i(INN)
=
0.5 dBFS; V
ref(fs)
=V
CCA
1.87 V; V
I(cm)
=V
CCA
1.95 V; typical values measured at
V
CCA
=V
CCD
=5V, V
CCO
= 3.3 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supplies
VCCA analog supply voltage 4.75 5.0 5.25 V
VCCD digital supply voltage 4.75 5.0 5.25 V
VCCO output supply voltage 2.7 3.3 3.6 V
ICCA analog supply current - 120 135 mA
ICCD digital supply current - 50 65 mA
ICCO output supply current fclk = 80 MHz;
fi=93MHz -1015mA
Ptot total power dissipation fclk = 80 MHz; DC input - 840 990 mW
Clock inputs: pins CLK and CLKN[1]
VIL LOW-level input voltage referenced to DGND; VCCD =5V
Positive
Emitter-Coupled
Logic (PECL) mode
3.19 - 3.52 V
Transistor-Transistor
Logic (TTL) mode DGND - 0.8 V
VIH HIGH-level input voltage referenced to DGND; VCCD =5V
PECL mode 3.83 - 4.12 V
TTL mode 2.0 - VCCD V
IIL LOW-level input current VCLK or VCLKN = 3.52 V [2] -- 28µA
VCLK or VCLKN = 0.80 V 1 - - nA
IIH HIGH-level input current VCLK or VCLKN = 3.83 V - - 30 µA
VCLK or VCLKN = 2.00 V 2 - - nA
Vi(clk)dif differential clock input
voltage VCLK VCLKN;
AC mode; DC voltage
level is 2.5 V
1.3 1.5 1.7 V
Riinput resistance fclk =80MHz [2] - 6.3 - k
Ciinput capacitance fclk =80MHz [2] - 1.1 - fF
Analog inputs: pins IN and INN
IIL LOW-level input current Vref(fs) =V
CCA 1.75 V - 5 - µA
IIH HIGH-level input current Vref(fs) =V
CCA 1.75 V - 5 - µA
Riinput resistance [2] 6.3 - - M
Ciinput capacitance [2] - - 700 fF
VI(cm) common-mode input
voltage Vi(IN) =V
i(INN);
output code = 2047 VCCA 2V
CCA 1.8 VCCA 1.6 V
Digital inputs: pins OTC and CE_N
VIL LOW-level input voltage DGND - 0.3 ×VCCD V
VIH HIGH-level input voltage 0.7 × VCCD -V
CCD V
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 7 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
IIL LOW-level input current VIL = 0.8 V - 1 - µA
IIH HIGH-level input current VIH = 2.0 V - 1 - µA
Digital inputs: pins DEL0 and DEL1
VIL LOW-level input voltage DGND - 0.3 ×VCCD V
VIH HIGH-level input voltage 0.7 × VCCD -V
CCD V
IIL LOW-level input current VIL = 0.8 V - 8 - µA
IIH HIGH-level input current VIH = 2.0 V - 20 - µA
Voltage controlled regulator output: pin CMADC
VO(cm) common-mode output
voltage IL=0mA - V
CCA 1.88 - V
IL=2mA - V
CCA 1.95 - V
Reference voltage input: pin FSIN[3]
Vref(fs) full-scale reference
voltage -V
CCA 1.80 - V
Iref(fs) full-scale reference
current - 0.1 - µA
Vi(a)(p-p) peak-to-peak analog
input voltage see Figure 5;
Vi=V
i(IN) Vi(INN);
VI(cm) =V
CCA 1.95 V
- 1.85 - V
Full-scale voltage controlled regulator output: pin FSOUT
VO(ref) reference output voltage IL=I
ref(fs) -V
CCA 1.80 - V
IL = 2 mA - VCCA 1.82 - V
Digital outputs: pins D11 to D0, IR and CCS
Output levels
VOL LOW-level output
voltage IOL = 2 mA DGND - DGND + 0.5 V
VOH HIGH-level output
voltage IOH =0.4 mA VCCO 0.5 - VCCO V
IOZ OFF-state output
current output level between
0.5 V and VCCO
0.1 0 +0.1 µA
Timing[4]
td(s) sampling delay time CL= 10 pF - 0.1 0.24 ns
th(o) output hold time CL= 10 pF 2.6 3.8 - ns
td(o) output delay time CL= 10 pF - 4.7 7.8 ns
3-state output delay
tdZH float to active HIGH
delay time - 3.6 - ns
tdZL float to active LOW
delay time - 3.9 - ns
tdHZ active HIGH to float
delay time - 9.2 - ns
tdLZ active LOW to float
delay time - 7.2 - ns
Table 5. Characteristics
…continued
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
40
°
C
to +85
°
C; V
i(IN)
V
i(INN)
=
0.5 dBFS; V
ref(fs)
=V
CCA
1.87 V; V
I(cm)
=V
CCA
1.95 V; typical values measured at
V
CCA
=V
CCD
=5V, V
CCO
= 3.3 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 8 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
Clock timing inputs: pins CLK and CLKN
δduty cycle fclk = 80 MHz;
fi= 175 MHz 45 - 55 %
fclk(min) minimum clock
frequency - - 9.5 MHz
fclk(max) maximum clock
frequency δ= 45 % to 55 % 80 - - MHz
Timing complete conversion signal: pin CCS; see Figure 6
td(CCS) CCS delay time CL= 10 pF;
DEL0 = HIGH;
DEL1 = LOW
- 0.3 - ns
CL= 10 pF;
DEL0 = LOW;
DEL1 = HIGH
- 1.3 - ns
CL=10pF;
DEL0 = HIGH;
DEL1 = HIGH
- 2.3 - ns
Analog signal processing (clock duty cycle 50 %)
INL integral non-linearity fclk = 20 MHz;
fi= 21.4 MHz -±2.0 - LSB
DNL differential non-linearity fclk = 20 MHz;
fi= 21.4 MHz; no
missing code
guaranteed
-±0.6 - LSB
Eoffset offset error VCCA =V
CCD =5V;
VCCO = 3.3 V;
Tamb =25°C;
output code = 2047
4 +8 +24 mV
EGgain error VCCA =V
CCD =5 V;
VCCO = 3.3 V;
Tamb =25°C
- 2.5 - %FS
B bandwidth fclk = 80 MHz; 3 dB;
full-scale input
[5] 320 375 - MHz
α2H second harmonic level fi= 21.4 MHz - 79 - dBc
fi= 93 MHz - 78 - dBc
fi= 175 MHz - 74 - dBc
α3H third harmonic level fi= 21.4 MHz - 84 - dBc
fi= 93 MHz - 80 - dBc
fi= 175 MHz - 76 - dBc
THD total harmonic distortion fi= 21.4 MHz [6] -75 - dBc
fi= 93 MHz - 73 - dBc
fi= 175 MHz - 68 - dBc
Nth(RMS) RMS thermal noise Vi(IN) =V
i(INN);
fclk =80MHz - 0.45 - LSB
Table 5. Characteristics
…continued
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
40
°
C
to +85
°
C; V
i(IN)
V
i(INN)
=
0.5 dBFS; V
ref(fs)
=V
CCA
1.87 V; V
I(cm)
=V
CCA
1.95 V; typical values measured at
V
CCA
=V
CCD
=5V, V
CCO
= 3.3 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 9 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
[1] The circuit has two clock inputs: CLK and CLKN. There are 5 modes of operation:
a) PECL mode 1: (DC levels vary 1:1 with VCCD) CLK and CLKN inputs are at differential PECL levels.
b) PECL mode 2: (DC levels vary 1:1 with VCCD) CLK input is at PECL level and sampling is taken on the falling edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLKN decoupled to GND via a 100 nF capacitor.
c) PECL mode 3: (DC levels vary 1:1 with VCCD) CLKN input is at PECL level and sampling is taken on the rising edge of the clock input
signal. A DC level of 3.65 V has to be applied on CLK decoupled to GND via a 100 nF capacitor.
d) Differential AC driving mode 4: When driving the CLK input directly and with any AC signal of minimum 1 V (p-p) and with a DC level
of 2.5 V, the sampling takes place at the falling edge of the clock signal. When driving the CLKN input with the same signal, sampling
takes place at the rising edge of the clock signal. It is recommended to decouple the CLKN or CLK input to DGND via a 100 nF
capacitor.
e) TTL mode 5: CLK input is at TTL level and sampling is taken on the falling edge of the clock input signal. In that case CLKN pin has
to be connected to the ground.
[2] Guaranteed by design.
[3] The ADC input range can be adjusted with an external reference connected to pin FSIN. This voltage has to be referenced to VCCA.
[4] Output data acquisition: the output data is available after the maximum delay of td(o).
[5] The 3 dB analog bandwidth is determined by the 3 dB reduction in the reconstructed output, the input being a full-scale sine wave.
[6] The total harmonic distortion is obtained with the addition of the first five harmonics.
[7] The signal-to-noise ratio takes into account all harmonics above five and noise up to Nyquist frequency.
[8] Intermodulation measured relative to either tone with analog input frequencies fi 1 and fi 2. The two input signals have the same
amplitude and the total amplitude of both signals provides full-scale to the converter (6 dB below full-scale for each input signal). IMD3
is the ratio of the RMS value of either input tone to the RMS value of the worst case third order intermodulation product; IMD2 is the ratio
of the RMS value of either input tone to the RMS value of the worst case second order intermodulation product.
S/N signal-to-noise ratio fi= 21.4 MHz [7] - 67.4 - dBc
fi= 93 MHz 63 67.2 - dBc
fi= 175 MHz - 66.5 - dBc
SFDR spurious free dynamic
range fi= 21.4 MHz - 76 - dBc
fi= 93 MHz 68 78 - dBc
fi= 175 MHz - 74 - dBc
ACPR adjacent channel power
ratio fi= 93 MHz; 5 MHz
channel spacing;
B = 3.84 MHz
-70- dB
IMD2 second-order
intermodulation
distortion
fi1 = 21 MHz;
fi2=22MHz
[8] -89 - dBFS
fi1 = 91.5 MHz;
fi2 = 94.5 MHz -86 - dBFS
fi1 = 174 MHz;
fi2 = 176 MHz -83 - dBFS
IMD3 third-order
intermodulation
distortion
fi1 = 21 MHz;
fi2=22MHz
[8] -88 - dBFS
fi1 = 91.5 MHz;
fi2 = 93.5 MHz -82 - dBFS
fi1 = 174 MHz;
fi2 = 176 MHz -83 - dBFS
Table 5. Characteristics
…continued
V
CCA
= 4.75 V to 5.25 V; V
CCD
= 4.75 V to 5.25 V; V
CCO
= 2.7 V to 3.6 V; AGND and DGND shorted together; T
amb
=
40
°
C
to +85
°
C; V
i(IN)
V
i(INN)
=
0.5 dBFS; V
ref(fs)
=V
CCA
1.87 V; V
I(cm)
=V
CCA
1.95 V; typical values measured at
V
CCA
=V
CCD
=5V, V
CCO
= 3.3 V, T
amb
=25
°
C and C
L
= 10 pF; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Tb
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 10 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
10. Additional information relating to Table 5
[1] X = don’t care.
Table 6. Output coding with differential inputs
V
i(IN)
V
i(INN)
= 1.9 V; V
ref(fs)
=V
CCA1
1.87 V; typical values to AGND.
Code Vi(IN) (V) Vi(INN) (V) IR Binary outputs
(D11 to D0) Two’s complement outputs
(D11 to D0)
Underflow < 2.675 > 3.625 0 0000 0000 0000 1000 0000 0000
0 2.675 3.625 1 0000 0000 0000 1000 0000 0000
1 - - 1 0000 0000 0001 1000 0000 0001
↓ ↓↓↓↓
2047 3.15 3.15 1 0111 1111 1111 1111 1111 1111
↓ ↓↓↓↓
4094 - - 1 1111 1111 1110 0111 1111 1110
4095 3.625 2.675 1 1111 1111 1111 0111 1111 1111
Overflow > 3.625 < 2.675 0 1111 1111 1111 0111 1111 1111
Table 7. Mode selection
Two’s complement output (OTC) Chip enable input (CE_N) Data output (D0 to D11; IR)
0 0 binary; active
1 0 two’s complement; active
X[1] 1 high-impedance
Fig 3. Output timing diagram
IN
CLK
0.5 V
n
D0 to D11
VCCO 0.5 V
50 %
data
n 1 data
ndata
n + 1
td(o)
td(s)
th(o)
014aaa432
sample
nsample
n + 1 sample
n + 2 sample
n + 3 sample
n + 4
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 11 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
The ADC1207S080 allows modifying the ADC full-scale. This could be done with FSIN
(full-scale input) according to Figure 5.
(1) fi1H = 15 MHz; 0 dBc
(2) fi 2H = 5.1 MHz; 79.6 dBc
(3) fi3H = 9.88 MHz; 82.1 dBc
(4) fi 4H = 20.1 MHz; 80.6 dBc
(5) fi 5H = 30 MHz; 74.7 dBc
(6) fi 6H = 35.1 MHz; 93.9 dBc
THD (5H): 72.2 dBc
SFDR: 74.7 dBc
Fig 4. Single tone; fi= 175 MHz; fCLK =80MHz
Fig 5. ADC full-scale; Vi(a)(p-p) as a function of Vref(fs)
fi (MHz)
0 40302010
014aaa435
80
120
40
0
power
spectrum
(dBc)
160
(1)
(5) (6)(4)(3)(2)
Vref(fs) (V)
1.4 2.22.01.81.6
014aaa436
1.8
1.6
2.0
2.2
Vi(a)(p-p)
(V)
1.4
W7 “(a 11m AM
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 12 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
The ADC1207S080 generates an adjustable clock output called Complete Conversion
Signal (CCS), which can be used to control the acquisition of converted output data by the
digital circuit connected to the ADC1207S080 output data bus. Two logic inputs, DEL0 and
DEL1 pins, allow adjusting the delay of the edge of the CCS signal to achieve an optimal
position in the stable, usable zone of the data.
Table 8. Complete conversion signal selection
DEL1 DEL0 CCS output
0 0 high-impedance
0 1 active, typical delay 0.3 ns
1 0 active, typical delay 1.3 ns
1 1 active, typical delay 2.3 ns
(1) td(CSS) is referenced to the middle of the active data.
Fig 6. Complete conversion signal timing diagram
014aaa433
D0 to D11
(1)
CCS
td(CCS)
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 13 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
11. Definitions
11.1 Static parameters
11.1.1 Integral Non-Linearity (INL)
It is defined as the deviation of the transfer function from a best fit straight line (linear
regression computation). The INL of the code i is obtained from the equation:
where: S corresponds to the slope of the ideal straight line (code width); i corresponds to
the code value; Vi is the input voltage.
11.1.2 Differential Non-Linearity (DNL)
It is the deviation in code width from the value of 1 LSB.
where: Vi is the input voltage; i from 0 to (2n 2).
11.2 Dynamic parameters
Figure 7 shows the spectrum of a single tone full-scale input sine wave with frequency f,
conforming to coherent sampling (f/fs= M/N, with M number of cycles and N number of
samples, M and N being relatively prime), and digitized by the ADC under test.
INL i() Vii() Viideal()
S
------------------------------------------
=
DNL i() Vii1+()Vii()
S
----------------------------------------
=
Fig 7. Single tone spectrum of full-scale input sine wave with frequency ft
a2
a1
magnitude
frequency
014aaa437
SFDR
ak
s
a3
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 14 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
Remark: In the following equations, Pnoise is the power of the terms which include the
effects of random noise, non-linearities, sampling time errors, and ‘quantization noise’.
11.2.1 SIgnal-to-Noise And Distortion (SINAD)
The ratio of the output signal power to the noise plus distortion power for a given sample
rate and input frequency, excluding the DC component:
11.2.2 Effective Number Of Bits (ENOB)
It is derived from SINAD and gives the theoretical resolution an ideal ADC would require
to obtain the same SINAD measured on the real ADC. A good approximation gives:
11.2.3 Total Harmonic Distortion (THD)
The ratio of the power of the harmonics to the power of the fundamental. For k 1
harmonics the THD is:
where:
The value of k is usually 6 (i.e. calculation of THD is done on the first 5 harmonics).
11.2.4 Signal-to-Noise ratio (S/N)
The ratio of the output signal power to the noise power, excluding the harmonics and the
DC component is:
11.2.5 Spurious Free Dynamic Range (SFDR)
The number SFDR specifies available signal range as the spectral distance between the
amplitude of the fundamental and the amplitude of the largest spurious harmonic and
non-harmonic, excluding DC component:
SINAD dB[] 10log10
Psignal
Pnoise distortion+
----------------------------------------


=
ENOB SINAD 1.76
6.02
----------------------------------
=
THD dB[] 10log10
Pharmonics
Psignal
-------------------------


=
Pharmonics α2
2α3
2…α
k
2
+++=
Psignal α1
2
=
SNdB[] 10log10
Psignal
Pnoise
----------------


=
SFDR dB[] 20log10
α1
max S()
------------------


=
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 15 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
11.2.6 IMD2 (IMD3)
From a dual tone input sinusoid (ft1 and ft2, these frequencies being chosen according to
the coherence criterion), the intermodulation distortion products IMD2 and IMD3
(respectively, 2nd and 3rd order components) are defined, as follows.
The ratio of the RMS value of either tone to the RMS value of the worst second (third)
order intermodulation product.
The total InterModulation Distortion (IMD) is given by:
where:
with corresponding to the power in the intermodulation component at frequency ft.
Fig 8. Spectral of dual tone input sine wave with frequency
f1 f2
2f2 f1
2f1 f2f1 + f2
2f22f1
f2f1
f1 + 2f2
3f2
2f1 + f2
3f1
magnitude
frequency
014aaa439
IMD dB[] 10log10
Pintermod
Psignal
----------------------


=
Pintermod αim ft1 ft2
()
2αim ft1 ft2
+()
2
αim ft1 2ft2
()
2αim ft1 2ft2
+()
2+++=
…α+im 2ft1 ft2
()
2αim 2ft1 ft2
+()
2
+
αim ft1
()
2
Psignal αft1
2αft2
2
+=
Tb
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 16 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
12. Application information
12.1 ADC1207S080 in 3G radio receivers
The ADC1207S080 has been proven in many 3G radio receivers with various operating
conditions regarding Input Frequency (IF), signal IF bandwidth and sampling frequency.
The ADC1207S080 is provided with a maximum analog input signal frequency of
400 MHz. It allows a significant cost-down of the RF front-end, from two mixers to only
one, even in multi-carriers architecture.
Table 9 describes some possible applications with the ADC1207S080 in high IF sampling
mode.
[1] IF bandwidth corresponds to the observed area on the ADC output spectrum.
For a dual carrier Wideband-Code-Division-Multiple-Access (W-CDMA) receiver, the most
important parameters are sensitivity and Adjacent Channel Selectivity (ACS). The
sensitivity is defined as the lowest detectable signal level. In W-CDMA, it can be far below
the noise floor. This difference, between the sensitivity and the noise floor, is defined by
the Sensitivity-to-Noise Ratio (SENR). Its value is negative due to the gain processing.
The Adjacent Channel Power Ratio (ACPR) is the difference between the full-scale 3dB
peak and the noise floor. It represents the ratio of the adjacent-channel power and the
average power level of the channel. The ACS is defined by the sum of SENR and ACPR.
Table 9. Examples of possible fi, fclk, IF BW combinations supported
fi (MHz) fclk (MHz) IF BW (MHz)[1] SNR (dB) SFDR (dBc)
350 80 5.00 65 71
243.95 9.60 0.25 71 80
96 76.80 1.60 72 76
96 76.80 4.80 71 77
96 76.80 20.00 68 76
80 61.44 10.00 70 85
78.4 44.80 3.50 71 76
70 40.00 1.25 72 79
Fig 9. Adjacent channel sensitivity and ADC sensibility
014aaa434
ACPR
NF
interfering channel wanted channel
ACS
noise floor
sensibility
thermal noise
SENR
3 / can at
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 17 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
12.2 Application diagram
Fig 10. Application diagram
014aaa438
36
ADC1207S080
DGND
35
D0
D1
34 D2
33 D3
32 D4
31 D5
30 D6
29 D7
28 D8
27 D9
26 D10
25 D11
37
CCS
38
DGND1
39
CLKN
40
CLK
VCCD1
4142
DGND1
43
AGND2
44
VCCA2
45
VCCA1
46
AGND1
47
VCCA1
48
AGND1
4
CMADC
5
INN
6
AGND1
7
DEC
8
n.c.
9
FSOUT
10
FSIN
11
n.c.
12
n.c.
242322212019181716151413
IR
VCCO
OGND
VCCO
OGND
OTC
CE_N
DGND2
VCCD2
DEL0
DEL1
n.c.
VCCD
330 nF 100 nF
4700_000_S (16) (41)
(44) (45) (47)
(21) (23)
10 nF 10 nF
VCCA
330 nF 100 nF
4700_000_S
HF70ACB
10 nF
OUT
ADJ
VCCO
100 nF 10 nF
10 nF
IN 32
1
LM317MDT
300
240
4.7 µF470 nF
10 V
5 V
GND
analog ground
1
2
n.c.
AGND1
VCCA VCCD
n.c.
100 nF
100 nF
CLK
TL431CPK
ADT1_1WT
VCCD1
3
5
1
6
2
4
50
VCCD VCCO
G1
3
IN
IN
10 nF 10 nF
digital ground
2
4
6
10 nF
10 nF
330 nF
100
100
2.2 k
ADT1_1WT
3
1
5
100 nF
100 nF
n.c.
XX
XX
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 18 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
13. Package outline
Fig 11. Package outline SOT545-2 (HTQFP48)
UNIT A
max. A1A2A3bpHDHELpZD(1) ZE(1)
ceLywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 1.2 0.15
0.05 1.05
0.95 0.25 0.27
0.17 0.20
0.09 7.1
6.9 0.5 9.1
8.9 0.9
0.6 7°
0°
0.08 0.080.21
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.75
0.45
SOT545-2 MS-026 03-04-07
04-01-29
D(1) E(1)
7.1
6.9 9.1
8.9
DhEh
4.6
4.4
4.6
4.4 0.9
0.6
bp
e
θ
EA1
A
Lp
detail X
L
B
121
48
37
D
H
bp
E
HA2
vMB
D
ZD
A
c
ZE
e
vMA
X
2536
24
13
y
pin 1 index
wM
wM
0 2.5 5 mm
scale
HTQFP48: plastic thermal enhanced thin quad flat package; 48 leads;
body 7 x 7 x 1 mm; exposed die pad SOT545-2
Dh
Eh
exposed die pad side
(A )
3
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 19 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
14. Revision history
Table 10. Revision history
Document ID Release date Data sheet status Change notice Supersedes
ADC1207S080_2 20080807 Product data sheet - ADC1207S080_1
Modifications: Corrections made to version number in Table 1.
Corrections made to several entries in Table 5.
Corrections made to alignment in Figure 10.
Corrections made to Figure 11.
ADC1207S080_1 20080611 Product data sheet - -
ADC1207S080_2 © NXP B.V. 2008. All rights reserved.
Product data sheet Rev. 02 — 7 August 2008 20 of 21
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
NXP Semiconductors ADC1207S080
Single 12 bits ADC, up to 80 MHz with direct/ultra high IF sampling
© NXP B.V. 2008. All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 7 August 2008
Document identifier: ADC1207S080_2
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
8 Thermal characteristics. . . . . . . . . . . . . . . . . . . 5
9 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 6
10 Additional information relating to Table 5 . . . 10
11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11.1 Static parameters . . . . . . . . . . . . . . . . . . . . . . 13
11.1.1 Integral Non-Linearity (INL) . . . . . . . . . . . . . . 13
11.1.2 Differential Non-Linearity (DNL) . . . . . . . . . . . 13
11.2 Dynamic parameters. . . . . . . . . . . . . . . . . . . . 13
11.2.1 SIgnal-to-Noise And Distortion (SINAD). . . . . 14
11.2.2 Effective Number Of Bits (ENOB). . . . . . . . . . 14
11.2.3 Total Harmonic Distortion (THD). . . . . . . . . . . 14
11.2.4 Signal-to-Noise ratio (S/N) . . . . . . . . . . . . . . . 14
11.2.5 Spurious Free Dynamic Range (SFDR) . . . . . 14
11.2.6 IMD2 (IMD3) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
12 Application information. . . . . . . . . . . . . . . . . . 16
12.1 ADC1207S080 in 3G radio receivers . . . . . . . 16
12.2 Application diagram . . . . . . . . . . . . . . . . . . . . 17
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 19
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
16 Contact information. . . . . . . . . . . . . . . . . . . . . 20
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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