MCIMX6(D,Q)PxEzzzz(A,B) Datasheet by NXP USA Inc.

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NXP Semiconductors
Data Sheet: Technical Data
Document Number: IMX6DQPCEC
Rev. 3, 11/2018
Package Information
FCPBGA Package
21 x 21 mm, 0.8 mm pitch
NXP Reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
See Table 1
MCIMX6QP5Exx1AA
MCIMX6QP5Exx1AB
MCIMX6DP5Exx1AA
MCIMX6DP5Exx1AB
MCIMX6QP5Exx2AA
MCIMX6QP5Exx2AB
MCIMX6DP5Exx2AA
MCIMX6DP5Exx2AB
1 Introduction
The i.MX 6DualPlus/6QuadPlus processors offer the
highest levels of graphics processing performance in the
i.MX 6 series family and are ideally suited for graphics
intensive applications.
The i.MX 6DualPlus/6QuadPlus processors feature
advanced implementation of the quad
Arm®Cortex®-A9 core, which operates at speeds up to
1.2 GHz. They include updated versions of the 2D and
3D graphics processors, 1080p video processing, and
integrated power management. Each processor provides
a 64-bit DDR3/DDR3L/LPDDR2 memory interface and
a number of other interfaces for connecting peripherals,
such as WLAN, Bluetooth®, GPS, hard drive, displays,
and camera sensors.
The i.MX 6DualPlus/6QuadPlus processors are
specifically useful for applications such as the
following:
Graphics rendering for Human Machine
Interfaces (HMI)
Video processing and display
i.MX 6DualPlus/6QuadPlus
Applications Processors
Consumer Products
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Signal Naming Convention . . . . . . . . . . . . . . . . . . . 7
2 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Modules List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Special Signal Considerations. . . . . . . . . . . . . . . . 19
3.2 Recommended Connections for Unused Analog
Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 Chip-Level Conditions . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Power Supplies Requirements and Restrictions . . 33
4.3 Integrated LDO Voltage Regulator Parameters . . 34
4.4 PLL Electrical Characteristics . . . . . . . . . . . . . . . . 36
4.5 On-Chip Oscillators . . . . . . . . . . . . . . . . . . . . . . . . 37
4.6 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 38
4.7 I/O AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 44
4.8 Output Buffer Impedance Parameters. . . . . . . . . . 49
4.9 System Modules Timing . . . . . . . . . . . . . . . . . . . . 53
4.10 Multi-Mode DDR Controller (MMDC). . . . . . . . . . . 64
4.11 General-Purpose Media Interface (GPMI) Timing. 64
4.12 External Peripheral Interface Parameters . . . . . . . 73
5 Boot Mode Configuration . . . . . . . . . . . . . . . . . . . . . . . 138
5.1 Boot Mode Configuration Pins. . . . . . . . . . . . . . . 138
5.2 Boot Devices Interfaces Allocation . . . . . . . . . . . 139
6 Package Information and Contact Assignments . . . . . . 141
6.1 Signal Naming Convention . . . . . . . . . . . . . . . . . 141
6.2 21 x 21 mm Package Information . . . . . . . . . . . . 141
7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
2NXP Semiconductors
Introduction
Netbooks (web tablets)
Nettops (Internet desktop devices)
High-end mobile Internet devices (MID)
High-end PDAs
High-end portable media players (PMP) with HD video capability
Gaming consoles
Portable navigation devices (PND)
The i.MX 6DualPlus/6QuadPlus processors offers numerous advanced features, such as:
Applications processors—The processors enhance the capabilities of high-tier portable
applications by fulfilling the ever increasing MIPS needs of operating systems and games. The
Dynamic Voltage and Frequency Scaling (DVFS) provides significant power reduction, allowing
the device to run at lower voltage and frequency with sufficient MIPS for tasks such as audio
decode.
Multilevel memory system—The multilevel memory system of each processor is based on the L1
instruction and data caches, L2 cache, and internal and external memory. The processors support
many types of external memory devices, including DDR3, DDR3L, LPDDR2, NOR Flash,
PSRAM, cellular RAM, NAND Flash (MLC and SLC), OneNAND™, and managed NAND,
including eMMC up to rev 4.4/4.41.
Smart speed technology—The processors have power management throughout the device that
enables the rich suite of multimedia features and peripherals to consume minimum power in both
active and various low power modes. Smart speed technology enables the designer to deliver a
feature-rich product, requiring levels of power far lower than industry expectations.
Dynamic voltage and frequency scaling—The processors improve the power efficiency of devices
by scaling the voltage and frequency to optimize performance.
Multimedia powerhouse—The multimedia performance of each processor is enhanced by a
multilevel cache system, Neon® MPE (Media Processor Engine) co-processor, a multi-standard
hardware video codec, 2 autonomous and independent image processing units (IPU), and a
programmable smart DMA (SDMA) controller.
Powerful graphics acceleration—Each processor provides three independent, integrated graphics
processing units: an OpenGL® ES 3.0 3D graphics accelerator with four shaders (up to 198 MTri/s
and OpenCL support), 2D graphics accelerator, and dedicated OpenVG™ 1.1 accelerator.
Interface flexibility—Each processor supports connections to a variety of interfaces: LCD
controller for up to four displays (including parallel display, HDMI1.4, MIPI display, and LVDS
display), dual CMOS sensor interface (parallel or through MIPI), high-speed USB on-the-go with
PHY, high-speed USB host with PHY, multiple expansion card ports (high-speed MMC/SDIO host
and other), 10/100/1000 Mbps Gigabit Ethernet controller, and a variety of other popular interfaces
(such as UART, I2C, and I2S serial audio, SATA-II, and PCIe-II).
Advanced security—The processors deliver hardware-enabled security features that enable secure
e-commerce, digital rights management (DRM), information encryption, secure boot, and secure
software downloads. The security features are discussed in detail in the i.MX 6Dual/6Quad
security reference manual (IMX6DQ6SDLSRM).
Introduction
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 3
Integrated power management—The processors integrate linear regulators and internally generate
voltage levels for different domains. This significantly simplifies system power management
structure.
1.1 Ordering Information
Table 1 shows examples of orderable part numbers covered by this data sheet. This table does not include
all possible orderable part numbers. The latest part numbers are available on nxp.com/imx6series. If your
desired part number is not listed in the table, or you have questions about available parts, see
nxp.com/imx6series or contact your NXP representative.
Figure 1 describes the part number nomenclature to identify the characteristics of the specific part number
you have (for example, cores, frequency, temperature grade, fuse options, silicon revision). Figure 1
applies to the i.MX 6DualPlus/6QuadPlus.
The two characteristics that identify which data sheet a specific part applies to are the part number series
field and the temperature grade (junction) field:
The i.MX 6DualPlus/6QuadPlus Automotive Applications Processors data sheet (IMX6DQPAEC)
covers parts listed for the “Plus” series and with “A” indicating automotive temperature.
•The
i.MX 6DualPlus/6QuadPlus
Applications Processors for Consumer Products data sheet
(IMX6DQPCEC) covers parts listed with “D (Commercial temp)” or “E (Extended Commercial
temp)”
The i.MX 6DualPlus/6QuadPlus Applications Processors for Industrial Products data sheet
(IMX6DQPIEC) covers parts listed with “C (Industrial temp)”
Table 1. Example Orderable Part Numbers
Part Number Quad/Dual CPU Options Speed1
1For 1 GHz speed grade: If a 24 MHz clock is used (required for USB), then the maximum SoC speed is limited to 996 MHz.
Temperature Grade Package
MCIMX6DP5EYM1AA i.MX 6DualPlus VPU, GPU 1GHz Extended commercial 21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6DP5EYM1AB i.MX 6DualPlus VPU, GPU 1 GHz Extended commercial 21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6QP5EYM1AA i.MX 6QuadPlus VPU, GPU 1GHz Extended commercial 21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6QP5EYM1AB i.MX 6QuadPlus VPU, GPU 1 GHz Extended commercial 21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (non-lidded)
MCIMX6DP5EVT2AA i.MX 6DualPlus VPU, GPU 1.2 GHz Extended commercial 21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
MCIMX6DP5EVT2AB i.MX 6DualPlus VPU, GPU 1.2 GHz Extended commercial 21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
MCIMX6QP5EVT2AA i.MX 6QuadPlus VPU, GPU 1.2 GHz Extended commercial 21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
MCIMX6QP5EVT2AB i.MX 6QuadPlus VPU, GPU 1.2 GHz Extended commercial 21 mm x 21 mm, 0.8 mm
pitch, FCPBGA (lidded)
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
4NXP Semiconductors
Introduction
Ensure that you have the right data sheet for your specific part by checking the fields: Part # Series
(DP/QP), temperature grade (junction) (A), and Frequency (8).
Figure 1. Part Number Nomenclature—i.MX 6DualPlus and i.MX 6QuadPlus
1.2 Features
The i.MX 6DualPlus/6QuadPlus processors are based on Arm Cortex-A9 MPCore platform, which has
the following features:
Arm Cortex-A9 MPCore 4xCPU processor (with TrustZone®)
The core configuration is symmetric, where each core includes:
32 KByte L1 Instruction Cache
32 KByte L1 Data Cache
Private Timer and Watchdog
Cortex-A9 NEON MPE (Media Processing Engine) Co-processor
The Arm Cortex-A9 MPCore complex includes:
General Interrupt Controller (GIC) with 128 interrupt support
Global Timer
Snoop Control Unit (SCU)
1 MB unified I/D L2 cache, shared by two/four cores
Two Master AXI (64-bit) bus interfaces output of L2 cache
Part differentiator @
Industrial with VPU, GPU, no MLB 7
Automotive with VPU, GPU 6
Consumer, with VPU, GPU 5
Automotive with GPU, no VPU 4 Temperature Tj +
Extended commercial: -20 to + 105°CE
Industrial: -40 to +105°CC
Automotive: -40 to + 125°CA
Frequency $
800 MHz1(Industrial grade) 8
852 MHz (Automotive grade) 8
1 GHz21
1.2 GHz 2
Package type RoHS
FCPBGA 21x21 0.8mm (lidded) VT
FCPBGA 21x21 0.8mm (non lidded) YM
Qualification level MC
Prototype Samples PC
Mass Production MC
Special SC
Part # series XX
i.MX 6QuadPlus QP
i.MX 6DualPlus DP
Silicon revision A
Rev 1.0 A
Rev 1.1 B
Fusing %
Real Codec off and no HDCP or DTCP A
MC IMX6 XX @+VV $%A
1. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 792 MHz.
2. If a 24 MHz input clock is used (required for USB), the maximum SoC speed is limited to 996 MHz.
Introduction
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 5
Frequency of the core (including Neon and L1 cache) as per Table 6.
NEON MPE coprocessor
SIMD Media Processing Architecture
NEON register file with 32x64-bit general-purpose registers
NEON Integer execute pipeline (ALU, Shift, MAC)
NEON dual, single-precision floating point execute pipeline (FADD, FMUL)
NEON load/store and permute pipeline
The SoC-level memory system consists of the following additional components:
Boot ROM, including HAB (96 KB)
Internal multimedia / shared, fast access RAM (OCRAM, 512 KB)
Secure/non-secure RAM (16 KB)
External memory interfaces:
16-bit, 32-bit, and 64-bit DDR3-1066, DDR3L-1066, and 1/2 LPDDR2-800 channels,
supporting DDR interleaving mode, for dual x32 LPDDR2
8-bit NAND-Flash, including support for Raw MLC/SLC, 2 KB, 4 KB, and 8 KB page size,
BA-NAND, PBA-NAND, LBA-NAND, OneNAND™ and others. BCH ECC up to 40 bit.
16/32-bit NOR Flash. All EIMv2 pins are muxed on other interfaces.
16/32-bit PSRAM, Cellular RAM
Each i.MX 6DualPlus/6QuadPlus processor enables the following interfaces to external devices (some of
them are muxed and not available simultaneously):
Hard Disk Drives—SATA II, 3.0 Gbps
Displays—Total five interfaces available. Total raw pixel rate of all interfaces is up to 450
Mpixels/sec, 24 bpp. Up to four interfaces may be active in parallel.
One Parallel 24-bit display port, up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual
HD1080 and WXGA at 60 Hz)
LVDS serial ports—One port up to 170 Mpixels/sec (for example, WUXGA at 60 Hz) or two
ports up to 85 MP/sec each
HDMI 1.4 port
MIPI/DSI, two lanes at 1 Gbps
Camera sensors:
Parallel Camera port (up to 20 bit and up to 240 MHz peak)
MIPI CSI-2 serial camera port, supporting up to 1000 Mbps/lane in 1/2/3-lane mode and up to
800 Mbps/lane in 4-lane mode. The CSI-2 Receiver core can manage one clock lane and up to
four data lanes. Each i.MX 6DualPlus/6QuadPlus processor has four lanes.
Expansion cards:
Four MMC/SD/SDIO card ports all supporting:
1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to UHS-I SDR-104
mode (104 MB/s max)
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
6NXP Semiconductors
Introduction
1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR
and DDR modes (104 MB/s max)
•USB:
One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY
Three USB 2.0 (480 Mbps) hosts:
One HS host with integrated High Speed PHY
Two HS hosts with integrated High Speed Inter-Chip (HS-IC) USB PHY
Expansion PCI Express port (PCIe) v2.0 one lane
PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint
operations. Uses x1 PHY configuration.
Miscellaneous IPs and interfaces:
SSI block capable of supporting audio sample frequencies up to 192 kHz stereo inputs and
outputs with I2S mode
ESAI is capable of supporting audio sample frequencies up to 260 kHz in I2S mode with
7.1 multi channel outputs
Five UARTs, up to 5.0 Mbps each:
Providing RS232 interface
Supporting 9-bit RS485 multidrop mode
One of the five UARTs (UART1) supports 8-wire while the other four support 4-wire. This
is due to the SoC IOMUX limitation, because all UART IPs are identical.
Five eCSPI (Enhanced CSPI)
Three I2C, supporting 400 kbps
Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps
Four Pulse Width Modulators (PWM)
System JTAG Controller (SJC)
GPIO with interrupt capabilities
8x8 Key Pad Port (KPP)
Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx
Two Controller Area Network (FlexCAN), 1 Mbps each
Two Watchdog timers (WDOG)
Audio MUX (AUDMUX)
MLB (MediaLB) provides interface to MOST Networks (150 Mbps)
The i.MX 6DualPlus/6QuadPlus processors integrate advanced power management unit and controllers:
Provide PMU, including LDO supplies, for on-chip resources
Use Temperature Sensor for monitoring the die temperature
Support DVFS techniques for low power modes
1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus
throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the
ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE).
Introduction
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 7
Use Software State Retention and Power Gating for Arm and MPE
Support various levels of system power modes
Use flexible clock gating control scheme
The i.MX 6DualPlus/6QuadPlus processors use dedicated hardware accelerators to meet the targeted
multimedia performance. The use of hardware accelerators is a key factor in obtaining high performance
at low power consumption numbers, while having the CPU core relatively free for performing other tasks.
The i.MX 6DualPlus/6QuadPlus processors incorporate the following hardware accelerators:
VPU—Video Processing Unit
IPUv3H—Image Processing Unit version 3H (2 IPUs)
GPU3Dv6—3D Graphics Processing Unit (OpenGL ES 3.0) version 6
GPU2Dv3—2D Graphics Processing Unit (BitBlt) version 3
GPUVG—OpenVG 1.1 Graphics Processing Unit
4 x PRE—Prefetch and Resolve Engine
2 x PRG—Prefetch and Resolve Gasket
ASRC—Asynchronous Sample Rate Converter
Security functions are enabled and accelerated by the following hardware:
Arm TrustZone including the TZ architecture (separation of interrupts, memory mapping, etc.)
SJC—System JTAG Controller. Protecting JTAG from debug port attacks by regulating or blocking
the access to the system debug features.
CAAM—Cryptographic Acceleration and Assurance Module, containing 16 KB secure RAM and
True and Pseudo Random Number Generator (NIST certified)
SNVS—Secure Non-Volatile Storage, including Secure Real Time Clock
CSU—Central Security Unit. Enhancement for the IC Identification Module (IIM). Will be
configured during boot and by eFUSEs and will determine the security level operation mode as
well as the TZ policy.
A-HAB—Advanced High Assurance Boot—HABv4 with the new embedded enhancements:
SHA-256, 2048-bit RSA key, version control mechanism, warm boot, CSU, and TZ initialization.
1.3 Signal Naming Convention
Throughout this document, the updated signal names are used except where referenced as a ball name
(such as the Functional Contact Assignments table, Ball Map table, and so on). A master list of the signal
name changes is in the document, IMX 6 Series Standardized Signal Name Map (EB792). This list can be
used to map the signal names used in older documentation to the new standardized naming conventions.
The signal names of the i.MX6 series of products are standardized to align the signal names within the
family and across the documentation. Benefits of this standardization are as follows:
Signal names are unique within the scope of an SoC and within the series of products
Searches will return all occurrences of the named signal
Signal names are consistent between i.MX 6 series products implementing the same modules
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
8NXP Semiconductors
Introduction
The module instance is incorporated into the signal name
This standardization applies only to signal names. The ball names are preserved to prevent the need to
change schematics, BSDL models, IBIS models, and so on.
MM V OCOTP \ \OMUXC \ KFF GFIO LAAAAAAJ LAAAAAAJ MLBISO [HHH HUI JHHH HSUMIP‘ EW>
Architectural Overview
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 9
2 Architectural Overview
The following subsections provide an architectural overview of the i.MX 6DualPlus/6QuadPlus
processor system.
2.1 Block Diagram
Figure 2 shows the functional modules in the i.MX 6DualPlus/6QuadPlus processor system.
Figure 2. i.MX 6DualPlus/6QuadPlusConsumer Grade System Block Diagram
NOTE
The numbers in brackets indicate number of module instances. For example,
PWM (4) indicates four separate PWM peripherals.
Smart DMA
(SDMA)
Shared Peripherals
AP Peripherals
ARM Cortex A9
SSI (3) eCSPI (5)
MPCore Platform
Timers/Control
GPT
PWM (4)
EPIT (2)
GPIO
WDOG (2)
I2C (3)
IOMUXC
OCOTP
AUDMUX
KPP
Boot
ROM
CSU
Fuse Box
Debug
DAP
TPIU
CAAM
(16KB Ram)
Security
USB OTG +
3 HS Ports
CTIs
Internal
Host PHY2
OTG PHY1
ESAI
External
Memory
RAM
(512KB)
LDB
1/2 LCD
Displays
Domain (AP)
SJC 1MB L2 cache
SCU, Timer
WLAN
USB OTG
JTAG
(IEEE1149.6)
Bluetooth
MMC/SD
eMMC/eSD
SATA II
3.0Gbps
GPS
Audio,
Power
Mgmnt.
SPBA
CAN (2)
Digital
Audio
5xFast-UART
SPDIF Rx/Tx
Video
Proc. Unit
(VPU + Cache)
3D Graphics
Proc. Unit
(GPU3D)
AXI and AHB Switch Fabric
1/2 LVDS
(WUXGA+)
Battery Ctrl
Device
NOR Flash
PSRAM
LPDDR2 (400 MHz)
DDR3 (532 MHz)
1-Gbps ENET
MLB 150
4x Camera
Parallel/MIPI
(96KB)
Clock and Reset
PLL (8)
CCM
GPC
SRC
XTALOSC
OSC32K
PTM’s CTI’s
HDMI 1.4
Display
GPMI
HSI/MIPI
MIPI
Display
DSI/MIPIHDMI
2xHSIC
PHY
PCIe Bus
ASRC
SNVS
(SRTC)
uSDHC (4)
Modem IC
2D Graphics
Proc. Unit
(GPU2D)
MMC/SD
SDXC
Raw/ONFI 2.2
Nand-Flash
MMDC
EIM
Keypad
A9-Core
L1 I/D Cache
Timer, Wdog
4x
Crystals
& Clock sources
ImageProcessing
Subsystem
2x IPUv3H
Temp Monitor
MLB/Most
OpenVG 1.1
Proc.
Unit
(GPU
VG)
Mbps
10/100/1000
Ethernet
Network
(dev/host)
Interface
2xCAN
Interface
GPSGPS
CSI2/MIPI
Application Processor
Power Management Unit
(PMU) LDOs
PRG PRE
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
10 NXP Semiconductors
Modules List
3 Modules List
The i.MX 6DualPlus/6QuadPlus processors contain a variety of digital and analog modules. Table 2
describes these modules in alphabetical order.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List
Block
Mnemonic Block Name Subsystem Brief Description
512 x 8 Fuse
Box
Electrical Fuse Array Security Electrical Fuse Array. Enables to setup Boot Modes, Security Levels,
Security Keys, and many other system parameters.
The i.MX 6DualPlus/6QuadPlus processors consist of 512x8-bit fuse box
accessible through OCOTP_CTRL interface.
APBH-DMA NAND Flash and
BCH ECC DMA
Controller
System
Control
Peripherals
DMA controller used for GPMI2 operation.
Arm Arm Platform Arm The Arm Cortex-A9 platform consists of 4x (four) Cortex-A9 cores version
r2p10 and associated sub-blocks, including Level 2 Cache Controller,
SCU (Snoop Control Unit), GIC (General Interrupt Controller), private
timers, Watchdog, and CoreSight debug modules.
ASRC Asynchronous
Sample Rate
Converter
Multimedia
Peripherals
The Asynchronous Sample Rate Converter (ASRC) converts the
sampling rate of a signal associated to an input clock into a signal
associated to a different output clock. The ASRC supports concurrent
sample rate conversion of up to 10 channels of about -120dB THD+N. The
sample rate conversion of each channel is associated to a pair of
incoming and outgoing sampling rates. The ASRC supports up to three
sampling rate pairs.
AUDMUX Digital Audio Mux Multimedia
Peripherals
The AUDMUX is a programmable interconnect for voice, audio, and
synchronous data routing between host serial interfaces (for example,
SSI1, SSI2, and SSI3) and peripheral serial interfaces (audio and voice
codecs). The AUDMUX has seven ports with identical functionality and
programming models. A desired connectivity is achieved by configuring
two or more AUDMUX ports.
BCH40 Binary-BCH ECC
Processor
System
Control
Peripherals
The BCH40 module provides up to 40-bit ECC error correction for NAND
Flash controller (GPMI).
CAAM Cryptographic
Accelerator and
Assurance Module
Security CAAM is a cryptographic accelerator and assurance module. CAAM
implements several encryption and hashing functions, a run-time integrity
checker, and a Pseudo Random Number Generator (PRNG). The pseudo
random number generator is certified by Cryptographic Algorithm
Validation Program (CAVP) of National Institute of Standards and
Technology (NIST). Its DRBG validation number is 94 and its SHS
validation number is 1455.
CAAM also implements a Secure Memory mechanism. In i.MX
6DualPlus/6QuadPlus processors, the security memory provided is 16
KB.
CCM
GPC
SRC
Clock Control
Module, General
Power Controller,
System Reset
Controller
Clocks,
Resets, and
Power Control
These modules are responsible for clock and reset distribution in the
system, and also for the system power management.
Modules List
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 11
CSI MIPI CSI-2 Interface Multimedia
Peripherals
The CSI IP provides MIPI CSI-2 standard camera interface port. The
CSI-2 interface supports up to 1 Gbps for up to 3 data lanes and up to 800
Mbps for 4 data lanes.
CSU Central Security Unit Security The Central Security Unit (CSU) is responsible for setting comprehensive
security policy within the i.MX 6DualPlus/6QuadPlus platform. The
Security Control Registers (SCR) of the CSU are set during boot time by
the HAB and are locked to prevent further writing.
CTI-0
CTI-1
CTI-2
CTI-3
CTI-4
Cross Trigger
Interfaces
Debug / Trace Cross Trigger Interfaces allows cross-triggering based on inputs from
masters attached to CTIs. The CTI module is internal to the Cortex-A9
Core Platform.
CTM Cross Trigger Matrix Debug / Trace Cross Trigger Matrix IP is used to route triggering events between CTIs.
The CTM module is internal to the Cortex-A9 Core Platform.
DAP Debug Access Port System
Control
Peripherals
The DAP provides real-time access for the debugger without halting the
core to:
System memory and peripheral registers
All debug configuration registers
The DAP also provides debugger access to JTAG scan chains. The DAP
module is internal to the Cortex-A9 Core Platform.
DCIC-0
DCIC-1
Display Content
Integrity Checker
Automotive IP The DCIC provides integrity check on portion(s) of the display. Each i.MX
6DualPlus/6QuadPlus processor has two such modules, one for each
IPU.
DSI MIPI DSI interface Multimedia
Peripherals
The MIPI DSI IP provides DSI standard display port interface. The DSI
interface support 80 Mbps to 1 Gbps speed per data lane.
eCSPI1-5 Configurable SPI Connectivity
Peripherals
Full-duplex enhanced Synchronous Serial Interface. It is configurable to
support Master/Slave modes, four chip selects to support multiple
peripherals.
ENET Ethernet Controller Connectivity
Peripherals
The Ethernet Media Access Controller (MAC) is designed to support
10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external
transceiver interface and transceiver function are required to complete the
interface to the media. The i.MX 6DualPlus/6QuadPlus processors also
consist of hardware assist for IEEE 1588 standard. For details, see the
ENET chapter of the i.MX 6DualPlus/6QuadPlus reference manual
(IMX6DQPRM).
Note: The theoretical maximum performance of 1 Gbps ENET is limited
to 470 Mbps (total for Tx and Rx) due to internal bus throughput
limitations. The actual measured performance in optimized environment
is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX
6Dual/6Quad errata document (IMX6DQCE).
EPIT-1
EPIT-2
Enhanced Periodic
Interrupt Timer
Timer
Peripherals
Each EPIT is a 32-bit “set and forget” timer that starts counting after the
EPIT is enabled by software. It is capable of providing precise interrupts
at regular intervals with minimal processor intervention. It has a 12-bit
prescaler for division of input clock frequency to get the required time
setting for the interrupts to occur, and counter value can be programmed
on the fly.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
12 NXP Semiconductors
Modules List
ESAI Enhanced Serial
Audio Interface
Connectivity
Peripherals
The Enhanced Serial Audio Interface (ESAI) provides a full-duplex serial
port for serial communication with a variety of serial devices, including
industry-standard codecs, SPDIF transceivers, and other processors.
The ESAI consists of independent transmitter and receiver sections, each
section with its own clock generator. All serial transfers are synchronized
to a clock. Additional synchronization signals are used to delineate the
word frames. The normal mode of operation is used to transfer data at a
periodic rate, one word per period. The network mode is also intended for
periodic transfers; however, it supports up to 32 words (time slots) per
period. This mode can be used to build time division multiplexed (TDM)
networks. In contrast, the on-demand mode is intended for non-periodic
transfers of data and to transfer data serially at high speed when the data
becomes available.
The ESAI has 12 pins for data and clocking connection to external
devices.
FlexCAN-1
FlexCAN-2
Flexible Controller
Area Network
Connectivity
Peripherals
The CAN protocol was primarily, but not only, designed to be used as a
vehicle serial data bus, meeting the specific requirements of this field:
real-time processing, reliable operation in the Electromagnetic
interference (EMI) environment of a vehicle, cost-effectiveness and
required bandwidth. The FlexCAN module is a full implementation of the
CAN protocol specification, Version 2.0 B, which supports both standard
and extended message frames.
GPIO-1
GPIO-2
GPIO-3
GPIO-4
GPIO-5
GPIO-6
GPIO-7
General Purpose I/O
Modules
System
Control
Peripherals
Used for general purpose input/output to external devices. Each GPIO
module supports 32 bits of I/O.
GPMI General Purpose
Media Interface
Connectivity
Peripherals
The GPMI module supports up to 8x NAND devices. 40-bit ECC error
correction for NAND Flash controller (GPMI2). The GPMI supports
separate DMA channels per NAND device.
GPT General Purpose
Timer
Timer
Peripherals
Each GPT is a 32-bit “free-running” or “set and forget” mode timer with
programmable prescaler and compare and capture register. A timer
counter value can be captured using an external event and can be
configured to trigger a capture event on either the leading or trailing edges
of an input pulse. When the timer is configured to operate in “set and
forget” mode, it is capable of providing precise interrupts at regular
intervals with minimal processor intervention. The counter has output
compare logic to provide the status and interrupt at comparison. This
timer can be configured to run either on an external clock or on an internal
clock.
GPU2Dv3 Graphics Processing
Unit-2D, ver. 3
Multimedia
Peripherals
The GPU2Dv3 provides hardware acceleration for 2D graphics
algorithms, such as Bit BLT, stretch BLT, and many other 2D functions.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
Modules List
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 13
GPU3Dv6 Graphics Processing
Unit-3D, ver. 6
Multimedia
Peripherals
The GPU2Dv6 provides hardware acceleration for 3D graphics algorithms
with sufficient processor power to run desktop quality interactive graphics
applications on displays up to HD1080 resolution. The GPU3D provides
OpenGL ES 3.0, including extensions, OpenGL ES 2.0, OpenGL ES 1.1,
and OpenVG 1.1
GPUVGv2 Vector Graphics
Processing Unit,
ver. 2
Multimedia
Peripherals
OpenVG graphics accelerator provides OpenVG 1.1 support as well as
other accelerations, including Real-time hardware curve tesselation of
lines, quadratic and cubic Bezier curves, 16x Line Anti-aliasing, and
various Vector Drawing functions.
HDMI Tx HDMI Tx interface Multimedia
Peripherals
The HDMI module provides HDMI standard interface port to an HDMI 1.4
compliant display.
HSI MIPI HSI interface Connectivity
Peripherals
The MIPI HSI provides a standard MIPI interface to the applications
processor.
I2C-1
I2C-2
I2C-3
I2C Interface Connectivity
Peripherals
I2C provide serial interface for external devices. Data rates of up to 400
kbps are supported.
IOMUXC IOMUX Control System
Control
Peripherals
This module enables flexible IO multiplexing. Each IO pad has default and
several alternate functions. The alternate functions are software
configurable.
IPUv3H-1
IPUv3H-2
Image Processing
Unit, ver. 3H
Multimedia
Peripherals
IPUv3H enables connectivity to displays and video sources, relevant
processing and synchronization and control capabilities, allowing
autonomous operation.
The IPUv3H supports concurrent output to two display ports and
concurrent input from two camera ports, through the following interfaces:
Parallel Interfaces for both display and camera
Single/dual channel LVDS display interface
HDMI transmitter
MIPI/DSI transmitter
MIPI/CSI-2 receiver
The processing includes:
Image conversions: resizing, rotation, inversion, and color space
conversion
A high-quality de-interlacing filter
Video/graphics combining
Image enhancement: color adjustment and gamut mapping, gamma
correction, and contrast enhancement
Support for display backlight reduction
KPP Key Pad Port Connectivity
Peripherals
KPP Supports 8 x 8 external key pad matrix. KPP features are:
Open drain design
Glitch suppression circuit design
Multiple keys detection
Standby key press detection
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
14 NXP Semiconductors
Modules List
LDB LVDS Display Bridge Connectivity
Peripherals
LVDS Display Bridge is used to connect the IPU (Image Processing Unit)
to External LVDS Display Interface. LDB supports two channels; each
channel has following signals:
One clock pair
Four data pairs
Each signal pair contains LVDS special differential pad (PadP, PadM).
MLB150 MediaLB Connectivity /
Multimedia
Peripherals
The MLB interface module provides a link to a MOST® data network,
using the standardized MediaLB protocol (up to 150 Mbps).
The module is backward compatible to MLB-50.
MMDC Multi-Mode DDR
Controller
Connectivity
Peripherals
DDR Controller has the following features:
Supports 16/32/64-bit DDR3 / DDR3L or LPDDR2
Supports both dual x32 for LPDDR2 and x64 DDR3 / LPDDR2
configurations (including 2x32 interleaved mode)
Supports LPDDR2 up to 400 MHz and DDR3 up to 532 MHz
Supports up to 4 GByte DDR memory space
OCOTP_CTRL OTP Controller Security The On-Chip OTP controller (OCOTP_CTRL) provides an interface for
reading, programming, and/or overriding identification and control
information stored in on-chip fuse elements. The module supports
electrically-programmable poly fuses (eFUSEs). The OCOTP_CTRL also
provides a set of volatile software-accessible signals that can be used for
software control of hardware elements, not requiring non-volatility. The
OCOTP_CTRL provides the primary user-visible mechanism for
interfacing with on-chip fuse elements. Among the uses for the fuses are
unique chip identifiers, mask revision numbers, cryptographic keys, JTAG
secure mode, boot characteristics, and various control signals, requiring
permanent non-volatility.
OCRAM On-Chip Memory
Controller
Data Path The On-Chip Memory controller (OCRAM) module is designed as an
interface between system’s AXI bus and internal (on-chip) SRAM memory
module.
In i.MX 6DualPlus/6QuadPlus processors, the OCRAM is used for
controlling the 512 KB multimedia RAM through a 64-bit AXI bus.
OSC 32 kHz OSC 32 kHz Clocking Generates 32.768 kHz clock from an external crystal.
PCIe PCI Express 2.0 Connectivity
Peripherals
The PCIe IP provides PCI Express Gen 2.0 functionality.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
Modules List
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 15
PRE1
PRE2
PRE3
PRE4
Prefetch/Resolve
Engine
Multimedia
Peripherals
The PRE includes the Resolve engine, Prefetch engine, and Store engine
3 blocks.The PRE key features are:
The Resolve engine supports:
GPU 32bpp 4x4 standard tile, 4x4 split tile, 4x4 super tile, 4x4 super
split tile format.
GPU 16bpp 8x4 standard tile, 8x4 split tile, 8x4 super tile, 8x4 super
split format.
32/16x4 block mode and scan mode.
The prefetch engine supports:
Transfer of non-interleaved YUV422(NI422), non-interleaved
YUV420(NI420), partial interleaved YUV422(PI422), and partial
interleaved YUV420(PI420), inputs to interleaved YUV422.
Vertical flip function both in block mode and scan mode. In block mode,
vertical flip function should complete with TPR module enable.
8bpp, 16bpp, 32bpp and 64bpp data format as generic data.
Transfer of non-interleaved YUV444(NI444), input to interleaved
YUV444 output.
The store Engine supports: 4/8/16 lines handshake modes with PRG.
PRG1
PRG2
Prefetch/Resolve
Gasket
Multimedia
Peripherals
The PRG is a digital core function which works as a gasket interface
between the fabric and the IPU system. The primary function is to re-map
the ARADDR from a frame-based address to a band-based address
depending on the different ARIDs. The PRG also implements the
handshake logic with the Prefetch Resolve Engine (PRE).
PMU Power-Management
Functions
Data Path Integrated power management unit. Used to provide power to various
SoC domains.
PWM-1
PWM-2
PWM-3
PWM-4
Pulse Width
Modulation
Connectivity
Peripherals
The pulse-width modulator (PWM) has a 16-bit counter and is optimized
to generate sound from stored sample audio images and it can also
generate tones. It uses 16-bit resolution and a 4x16 data FIFO to generate
sound.
RAM
16 KB
Secure/non-secure
RAM
Secured
Internal
Memory
Secure/non-secure Internal RAM, interfaced through the CAAM.
RAM
512 KB
Internal RAM Internal
Memory
Internal RAM, which is accessed through OCRAM memory controllers.
ROM
96 KB
Boot ROM Internal
Memory
Supports secure and regular Boot Modes. Includes read protection on 4K
region for content protection
SATA Serial ATA Connectivity
Peripherals
The SATA controller and PHY is a complete mixed-signal IP solution
designed to implement SATA II, 3.0 Gbps HDD connectivity.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
16 NXP Semiconductors
Modules List
SDMA Smart Direct Memory
Access
System
Control
Peripherals
The SDMA is multi-channel flexible DMA engine. It helps in maximizing
system performance by off-loading the various cores in dynamic data
routing. It has the following features:
Powered by a 16-bit Instruction-Set micro-RISC engine
Multi-channel DMA supporting up to 32 time-division multiplexed DMA
channels
48 events with total flexibility to trigger any combination of channels
Memory accesses including linear, FIFO, and 2D addressing
Shared peripherals between Arm and SDMA
Very fast context-switching with 2-level priority based preemptive
multi-tasking
DMA units with auto-flush and prefetch capability
Flexible address management for DMA transfers (increment,
decrement, and no address changes on source and destination
address)
DMA ports can handle unit-directional and bi-directional flows (copy
mode)
Up to 8-word buffer for configurable burst transfers
Support of byte-swapping and CRC calculations
Library of Scripts and API is available
SJC System JTAG
Controller
System
Control
Peripherals
The SJC provides JTAG interface, which complies with JTAG TAP
standards, to internal logic. The i.MX 6DualPlus/6QuadPlus processors
use JTAG port for production, testing, and system debugging. In addition,
the SJC provides BSR (Boundary Scan Register) standard support, which
complies with IEEE1149.1 and IEEE1149.6 standards.
The JTAG port must be accessible during platform initial laboratory
bring-up, for manufacturing tests and troubleshooting, as well as for
software debugging by authorized entities. The i.MX
6DualPlus/6QuadPlus SJC incorporates three security modes for
protecting against unauthorized accesses. Modes are selected through
eFUSE configuration.
SNVS Secure Non-Volatile
Storage
Security Secure Non-Volatile Storage, including Secure Real Time Clock, Security
State Machine, Master Key Control, and Violation/Tamper Detection and
reporting.
SPDIF Sony Philips Digital
Interconnect Format
Multimedia
Peripherals
A standard audio file transfer format, developed jointly by the Sony and
Phillips corporations. It supports Transmitter and Receiver functionality.
SSI-1
SSI-2
SSI-3
I2S/SSI/AC97
Interface
Connectivity
Peripherals
The SSI is a full-duplex synchronous interface, which is used on the
processor to provide connectivity with off-chip audio peripherals. The SSI
supports a wide variety of protocols (SSI normal, SSI network, I2S, and
AC-97), bit depths (up to 24 bits per word), and clock / frame sync options.
The SSI has two pairs of 8x24 FIFOs and hardware support for an
external DMA controller to minimize its impact on system performance.
The second pair of FIFOs provides hardware interleaving of a second
audio stream that reduces CPU overhead in use cases where two time
slots are being used simultaneously.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
Modules List
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 17
TEMPMON Temperature Monitor System
Control
Peripherals
The temperature monitor/sensor IP module for detecting high temperature
conditions. The temperature read out does not reflect case or ambient
temperature. It reflects the temperature in proximity of the sensor location
on the die. Temperature distribution may not be uniformly distributed;
therefore, the read out value may not be the reflection of the temperature
value for the entire die.
TZASC Trust-Zone Address
Space Controller
Security The TZASC (TZC-380 by Arm) provides security address region control
functions required for intended application. It is used on the path to the
DRAM controller.
UART-1
UART-2
UART-3
UART-4
UART-5
UART Interface Connectivity
Peripherals
Each of the UARTv2 modules support the following serial data
transmit/receive protocols and configurations:
7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd
or none)
Programmable baud rates up to 5 MHz
32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting auto-baud
IrDA 1.0 support (up to SIR speed of 115200 bps)
Option to operate as 8-pins full UART, DCE, or DTE
USBOH3A USB 2.0 High Speed
OTG and 3x HS
Hosts
Connectivity
Peripherals
USBOH3 contains:
One high-speed OTG module with integrated HS USB PHY
One high-speed Host module with integrated HS USB PHY
Two identical high-speed Host modules connected to HSIC USB ports.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
18 NXP Semiconductors
Modules List
uSDHC-1
uSDHC-2
uSDHC-2
uSDHC-4
SD/MMC and SDXC
Enhanced
Multi-Media Card /
Secure Digital Host
Controller
Connectivity
Peripherals
i.MX 6DualPlus/6QuadPlus specific SoC characteristics:
All four MMC/SD/SDIO controller IPs are identical and are based on the
uSDHC IP. They are:
Conforms to the SD Host Controller Standard Specification version 3.0
Fully compliant with MMC command/response sets and Physical Layer
as defined in the Multimedia Card System Specification,
v4.2/4.3/4.4/4.41 including high-capacity (size > 2 GB) cards HC MMC.
Hardware reset as specified for eMMC cards is supported at ports #3
and #4 only.
Fully compliant with SD command/response sets and Physical Layer
as defined in the SD Memory Card Specifications, v3.0 including
high-capacity SDHC cards up to 32 GB and SDXC cards up to 2TB.
Fully compliant with SDIO command/response sets and
interrupt/read-wait mode as defined in the SDIO Card Specification,
Part E1, v1.10
Fully compliant with SD Card Specification, Part A2, SD Host
Controller Standard Specification, v2.00
All four ports support:
1-bit or 4-bit transfer mode specifications for SD and SDIO cards up to
UHS-I SDR104 mode (104 MB/s max)
1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52
MHz in both SDR and DDR modes (104 MB/s max)
However, the SoC-level integration and I/O muxing logic restrict the
functionality to the following:
Instances #1 and #2 are primarily intended to serve as external slots or
interfaces to on-board SDIO devices. These ports are equipped with
“Card Detection” and “Write Protection” pads and do not support
hardware reset.
Instances #3 and #4 are primarily intended to serve interfaces to
embedded MMC memory or interfaces to on-board SDIO devices.
These ports do not have “Card detection” and “Write Protection” pads
and do support hardware reset.
All ports can work with 1.8 V and 3.3 V cards. There are two completely
independent I/O power domains for Ports #1 and #2 in four bit
configuration (SD interface). Port #3 is placed in his own independent
power domain and port #4 shares power domain with some other
interfaces.
VDOA VDOA Multimedia
Peripherals
The Video Data Order Adapter (VDOA) is used to re-order video data from
the “tiled” order used by the VPU to the conventional raster-scan order
needed by the IPU.
VPU Video Processing
Unit
Multimedia
Peripherals
A high-performing video processing unit (VPU), which covers many
SD-level and HD-level video decoders and SD-level encoders as a
multi-standard video codec engine as well as several important video
processing, such as rotation and mirroring.
See the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM) for
complete list of VPU’s decoding/encoding capabilities.
WDOG-1 Watchdog Timer
Peripherals
The Watchdog Timer supports two comparison points during each
counting period. Each of the comparison points is configurable to evoke
an interrupt to the Arm core, and a second point evokes an external event
on the WDOG line.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
Modules List
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 19
3.1 Special Signal Considerations
The package contact assignments can be found in Section 6, “Package Information and Contact
Assignments.” Signal descriptions are defined in the i.MX 6DualPlus/6QuadPlus reference manual
(IMX6DQPRM). Special signal consideration information is contained in the Hardware Development
Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors
(IMX6DQ6SDLHDG).
3.2 Recommended Connections for Unused Analog Interfaces
The recommended connections for unused analog interfaces can be found in the section, “Unused analog
interfaces,” of the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of
Applications Processors (IMX6DQ6SDLHDG).
WDOG-2
(TZ)
Watchdog
(TrustZone)
Timer
Peripherals
The TrustZone Watchdog (TZ WDOG) timer module protects against
TrustZone starvation by providing a method of escaping normal mode and
forcing a switch to the TZ mode. TZ starvation is a situation where the
normal OS prevents switching to the TZ mode. Such a situation is
undesirable as it can compromise the system’s security. Once the TZ
WDOG module is activated, it must be serviced by TZ software on a
periodic basis. If servicing does not take place, the timer times out. Upon
a time-out, the TZ WDOG asserts a TZ mapped interrupt that forces
switching to the TZ mode. If it is still not served, the TZ WDOG asserts a
security violation signal to the CSU. The TZ WDOG module cannot be
programmed or deactivated by a normal mode Software.
EIM NOR-Flash /PSRAM
interface
Connectivity
Peripherals
The EIM NOR-FLASH / PSRAM provides:
Support 16-bit (in muxed IO mode only) PSRAM memories (sync and
async operating modes), at slow frequency
Support 16-bit (in muxed IO mode only) NOR-Flash memories, at slow
frequency
Multiple chip selects
XTALOSC Crystal Oscillator
interface
The XTALOSC module enables connectivity to external crystal oscillator
device. In a typical application use-case, it is used for 24 MHz oscillator.
Table 2. i.MX 6DualPlus/6QuadPlus Modules List (continued)
Block
Mnemonic Block Name Subsystem Brief Description
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
20 NXP Semiconductors
Electrical Characteristics
4 Electrical Characteristics
This section provides the device and module-level electrical characteristics for the i.MX
6DualPlus/6QuadPlus processors.
4.1 Chip-Level Conditions
This section provides the device-level electrical characteristics for the SoC. See Table 3 for a quick
reference to the individual tables and sections.
4.1.1 Absolute Maximum Ratings
CAUTION
Stresses beyond those listed under Table 4 may affect reliability or cause
permanent damage to the device. These are stress ratings only. Functional
operation of the device at these or any other conditions beyond those
indicated in the Operating Ranges or Parameters tables is not implied.
Table 3. i.MX 6DualPlus/6QuadPlus Chip-Level Conditions
For these characteristics, Topic appears …
Absolute Maximum Ratings on page 21
FCPBGA Package Thermal Resistance on page 22
Operating Ranges on page 23
External Clock Sources on page 25
Maximum Measured Supply Currents on page 27
Low Power Mode Supply Currents on page 28
USB PHY Current Consumption on page 30
SATA Typical Power Consumption on page 30
PCIe 2.0 Maximum Power Consumption on page 31
HDMI Maximum Power Consumption on page 32
‘ enme 1; \ um ; ovamow 99 “we ‘ )
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 21
Table 4. Absolute Maximum Ratings
Parameter Description Symbol Min Max Unit
Core supply input voltage (LDO enabled) VDD_ARM_IN
VDD_ARM23_IN
VDD_SOC_IN
-0.3 1.6 V
Core supply input voltage (LDO bypass) VDD_ARM_IN
VDD_ARM23_IN
VDD_SOC_IN
-0.3 1.4 V
Core supply output voltage (LDO enabled) VDD_ARM_CAP
VDD_SOC_CAP
VDD_PU_CAP
NVCC_PLL_OUT
-0.3 1.4 V
VDD_HIGH_IN supply voltage VDD_HIGH_IN -0.3 3.7 V
DDR I/O supply voltage NVCC_DRAM -0.4 1.975 (See note 1)
1The absolute maximum voltage includes an allowance for 400 mV of overshoot on the IO pins. Per JEDEC standards, the
allowed signal overshoot must be derated if NVCC_DRAM exceeds 1.575V.
V
GPIO I/O supply voltage NVCC_CSI
NVCC_EIM
NVCC_ENET
NVCC_GPIO
NVCC_LCD
NVCC_NAND
NVCC_SD
NVCC_JTAG
-0.5 3.7 V
HDMI, PCIe, and SATA PHY high (VPH) supply voltage HDMI_VPH
PCIE_VPH
SATA_VPH
-0.3 2.85 V
HDMI, PCIe, and SATA PHY low (VP) supply voltage HDMI_VP
PCIE_VP
SATA_VP
-0.3 1.4 V
LVDS, MLB, and MIPI I/O supply voltage (2.5V supply) NVCC_LVDS_2P5
NVCC_MIPI -0.3 2.85 V
PCIe PHY supply voltage PCIE_VPTX -0.3 1.4 V
RGMII I/O supply voltage NVCC_RGMII -0.5 2.725 V
SNVS IN supply voltage
(Secure Non-Volatile Storage and Real Time Clock)
VDD_SNVS_IN -0.3 3.4 V
USB I/O supply voltage USB_H1_DN
USB_H1_DP
USB_OTG_DN
USB_OTG_DP
USB_OTG_CHD_B
-0.3 3.73 V
USB VBUS supply voltage USB_H1_VBUS
USB_OTG_VBUS —5.35 V
Vin/Vout input/output voltage range (non-DDR pins) Vin/Vout -0.5 OVDD+0.3 (See note 2)
2OVDD is the I/O supply voltage.
V
Vin/Vout input/output voltage range (DDR pins) Vin/Vout -0.5 OVDD+0.4 (See notes1&2) V
ESD immunity (HBM) Vesd_HBM —2000 V
ESD immunity (CDM) Vesd_CDM — 500 V
Storage temperature range Tstorage -40 150 °C
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
22 NXP Semiconductors
Electrical Characteristics
4.1.2 Thermal Resistance
NOTE
Per JEDEC JESD51-2, the intent of thermal resistance measurements is
solely for a thermal performance comparison of one package to another in a
standardized environment. This methodology is not meant to and will not
predict the performance of a package in an application-specific
environment.
4.1.2.1 FCPBGA Package Thermal Resistance
Table 5 provides the FCPBGA package thermal resistance data for the non-lidded package type.
Table 5. FCPBGA Package Thermal Resistance Data (Non-Lidded)
Thermal Parameter Test Conditions Symbol Value Unit
Junction to Ambient1
1Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
Single-layer board (1s); natural convection2
2Per JEDEC JESD51-3 with the single layer board horizontal. Thermal test board meets JEDEC specification for the specified
package.
RθJA 31 °C/W
Four-layer board (2s2p); natural convection2RθJA 22 °C/W
Junction to Ambient1Single-layer board (1s); air flow 200 ft/min3
3Per JEDEC JESD51-6 with the board horizontal.
RθJMA 24 °C/W
Four-layer board (2s2p); air flow 200 ft/min3RθJMA 18 °C/W
Junction to Board1,4
4Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
—R
θJB 12 °C/W
Junction to Case (top)1,5
5Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1). The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the
interface layer.
—R
θJCtop <0.1 °C/W
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 23
4.1.3 Operating Ranges
Table 6 provides the operating ranges of the i.MX 6DualPlus/6QuadPlus processors.
Table 6. Operating Ranges
Parameter
Description Symbol Min Typ Max1Unit Comment2
Run mode:
LDO enabled
VDD_ARM_IN
VDD_ARM23_IN3
1.44 1.5 V LDO Output Set Point (VDD_ARM_CAP5) of
1.275 V minimum for operation up to 1200 MHz.
Only supported in LDO enabled mode.
1.354 1.5 V LDO Output Set Point (VDD_ARM_CAP5) of
1.225 V minimum for operation up to 996 MHz.
1.2754 1.5 V LDO Output Set Point (VDD_ARM_CAP5) of
1.150 V minimum for operation up to 792 MHz.
1.054 1.5 V LDO Output Set Point (VDD_ARM_CAP5) of
0.925 V minimum for operation up to 396 MHz.
VDD_SOC_IN61.354 1.5 V 264 MHz < VPU 352 MHz; VDDSOC and
VDDPU LDO outputs (VDD_SOC_CAP and
VDD_PU_CAP) require 1.225 V minimum.
1.2754,7 1.5 V VPU 264 MHz; VDDSOC and VDDPU LDO
outputs (VDD_SOC_CAP and VDD_PU_CAP)
require 1.15 V minimum.
Run mode:
LDO bypassed8
VDD_ARM_IN
VDD_ARM23_IN3
1.225 1.3 V LDO bypassed for operation up to 996 MHz.
1.150 1.3 V LDO bypassed for operation up to 792 MHz.
0.925 1.3 V LDO bypassed for operation up to 396 MHz.
VDD_SOC_IN61.225 1.3 V 264 MHz < VPU 352 MHz
1.15 1.3 V VPU 264 MHz
Standby/DSM mode VDD_ARM_IN
VDD_ARM23_IN3
0.9 1.3 V See Table 9, “Stop Mode Current and Power
Consumption,” on page 28.
VDD_SOC_IN 1.05 1.3 V
VDD_HIGH internal
regulator
VDD_HIGH_IN92.7 3.6 V Must match the range of voltages that the
rechargeable backup battery supports.
Backup battery supply
range
VDD_SNVS_IN92.8 3.6 V Should be supplied from the same supply as
VDD_HIGH_IN, if the system does not require
keeping real time and other data on OFF state.
USB supply voltages USB_OTG_VBUS 4.4 5.25 V
USB_H1_VBUS 4.4 5.25 V
DDR I/O supply NVCC_DRAM 1.14 1.2 1.3 V LPDDR2
1.425 1.5 1.575 V DDR3
1.283 1.35 1.45 V DDR3L
Supply for RGMII I/O
power group10
NVCC_RGMII 1.15 2.625 V 1.15 V – 1.30 V in HSIC 1.2 V mode
1.43 V – 1.58 V in RGMII 1.5 V mode
1.70 V – 1.90 V in RGMII 1.8 V mode
2.25 V – 2.625 V in RGMII 2.5 V mode
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
24 NXP Semiconductors
Electrical Characteristics
GPIO supplies10 NVCC_CSI,
NVCC_EIM0,
NVCC_EIM1,
NVCC_EIM2,
NVCC_ENET,
NVCC_GPIO,
NVCC_LCD,
NVCC_NANDF,
NVCC_SD1,
NVCC_SD2,
NVCC_SD3,
NVCC_JTAG
1.65 1.8,
2.8,
3.3
3.6 V Isolation between the NVCC_EIMx and
NVCC_SDx different supplies allow them to
operate at different voltages within the specified
range.
Example: NVCC_EIM1 can operate at 1.8 V
while NVCC_EIM2 operates at 3.3 V.
NVCC_LVDS_2P511
NVCC_MIPI
2.25 2.5 2.75 V
HDMI supply voltages HDMI_VP 0.99 1.1 1.3 V
HDMI_VPH 2.25 2.5 2.75 V
PCIe supply voltages PCIE_VP 1.023 1.1 1.3 V
PCIE_VPH 2.325 2.5 2.75 V
PCIE_VPTX 1.023 1.1 1.3 V
SATA Supply voltages SATA_VP 0.99 1.1 1.3 V
SATA_VPH 2.25 2.5 2.75 V
Junction temperature TJ-20 95 105 °CSee i.MX 6Dual/6Quad Product Lifetime Usage
Estimates Application Note, AN4724, for
information on product lifetime (power-on
years) for this processor.
1Applying the maximum voltage results in maximum power consumption and heat generation. NXP recommends a voltage set
point = (Vmin + the supply tolerance). This results in an optimized power/speed ratio.
2See the Hardware Development Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors
(IMX6DQ6SDLHDG) for bypass capacitors requirements for each of the *_CAP supply outputs.
3For Quad core system, connect to VDD_ARM_IN. For Dual core system, may be shorted to GND together with
VDD_ARM23_CAP to reduce leakage.
4VDD_ARM_IN and VDD_SOC_IN must be at least 125 mV higher than the LDO Output Set Point for correct voltage regulation.
5VDD_ARM_CAP must not exceed VDD_CACHE_CAP by more than +50 mV. VDD_CACHE_CAP must not exceed
VDD_ARM_CAP by more than 200 mV.
6VDD_SOC_CAP and VDD_PU_CAP must be equal.
7In LDO enabled mode, the internal LDO output set points must be configured such that the:
VDD_ARM LDO output set point does not exceed the VDD_SOC LDO output set point by more than 100 mV.
VDD_SOC LDO output set point is equal to the VDD_PU LDO output set point.
The VDD_ARM LDO output set point can be lower than the VDD_SOC LDO output set point, however, the minimum output set
points shown in this table must be maintained.
8In LDO bypassed mode, the external power supply must ensure that VDD_ARM_IN does not exceed VDD_SOC_IN by more
than 100 mV. The VDD_ARM_IN supply voltage can be lower than the VDD_SOC_IN supply voltage. The minimum voltages
shown in this table must be maintained.
9To set VDD_SNVS_IN voltage with respect to Charging Currents and RTC, see the Hardware Development Guide for i.MX
6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).
Table 6. Operating Ranges (continued)
Parameter
Description Symbol Min Typ Max1Unit Comment2
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 25
4.1.4 External Clock Sources
Each i.MX 6DualPlus/6QuadPlus processor has two external input system clocks: a low frequency
(RTC_XTALI) and a high frequency (XTALI).
The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,
power-down real time clock operation, and slow system and watchdog counters. The clock input can be
connected to either an external oscillator or a crystal using the internal oscillator amplifier. Additionally,
there is an internal ring oscillator, that can be used instead of RTC_XTALI when accuracy is not important.
The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other
peripherals. The system clock input can be connected to either an external oscillator or a crystal using the
internal oscillator amplifier.
NOTE
The internal RTC oscillator does not provide an accurate frequency and is
affected by process, voltage and temperature variations. NXP strongly
recommends using an external crystal as the RTC_XTALI reference. If the
internal oscillator is used instead, careful consideration should be given to
the timing implications on all of the SoC modules dependent on this clock.
Table 7 shows the interface frequency requirements.
The typical values shown in Table 7 are required for use with NXP BSPs to ensure precise time keeping
and USB operation. For RTC_XTALI operation, two clock sources are available:
On-chip 40 kHz ring oscillator: This clock source has the following characteristics:
Approximately 25 μA more Idd than crystal oscillator
Approximately ±50% tolerance
No external component required
Starts up quicker than 32 kHz crystal oscillator
External crystal oscillator with on-chip support circuit
10 All digital I/O supplies (NVCC_xxxx) must be powered under normal conditions whether the associated I/O pins are in use or
not, and associated I/O pins need to have a pull-up or pull-down resistor applied to limit any floating gate current.
11 This supply also powers the pre-drivers of the DDR I/O pins; therefore, it must always be provided, even when LVDS is not used.
Table 7. External Input Clock Frequency
Parameter Description Symbol Min Typ Max Unit
RTC_XTALI Oscillator1,2
1External oscillator or a crystal with internal oscillator amplifier.
2The required frequency stability of this clock source is application dependent. For recommendations, see the Hardware
Development Guide for i.MX 6Dual, 6Quad, 6Solo, 6DualLite Families of Applications Processors (IMX6DQ6SDLHDG).
fckil — 32.7683/32.0
3Recommended nominal frequency 32.768 kHz.
—kHz
XTALI Oscillator2,4
4External oscillator or a fundamental frequency crystal with internal oscillator amplifier.
fxtal —24MHz
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
26 NXP Semiconductors
Electrical Characteristics
At power up, an internal ring oscillator is used. After crystal oscillator is stable, the clock circuit
switches over to the crystal oscillator automatically.
Higher accuracy than ring oscillator.
If no external crystal is present, then the ring oscillator is used.
The decision to choose a clock source should be based on real-time clock use and precision timeout.
4.1.5 Maximum Measured Supply Currents
Power consumption is highly dependent on the application. Estimating the maximum supply currents
required for power supply design is difficult because the use case that requires maximum supply current is
not a realistic use case.
To help illustrate the effect of the application on power consumption, data was collected while running
industry standard benchmarks that are designed to be compute and graphic intensive. The results provided
are intended to be used as guidelines for power supply design.
Description of test conditions:
The Power Virus data shown in Table 8 represent a use case designed specifically to show the
maximum current consumption possible for the Arm core complex. All cores are running at the
defined maximum frequency and are limited to L1 cache accesses only to ensure no pipeline stalls.
Although a valid condition, it would have a very limited, if any, practical use case, and be limited
to an extremely low duty cycle unless the intention was to specifically cause the worst case power
consumption.
EEMBC CoreMark: Benchmark designed specifically for the purpose of measuring the
performance of a CPU core. More information available at www.eembc.org/coremark. Note that
this benchmark is designed as a core performance benchmark, not a power benchmark. This use
case is provided as an example of power consumption that would be typical in a
computationally-intensive application rather than the Power Virus.
3DMark Mobile 2011: Suite of benchmarks designed for the purpose of measuring graphics and
overall system performance. Note that this benchmark is designed as a graphics performance
benchmark, not a power benchmark. This use case is provided as an example of power
consumption that would be typical in a very graphics-intensive application.
Devices used for the tests were from the high current end of the expected process variation.
The NXP power management IC, MMPF0100xxxx, which is targeted for the i.MX 6 series processor
family, supports the power consumption shown in Table 8, however a robust thermal design is required for
the increased system power dissipation.
See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for more
details on typical power consumption under various use case definitions.
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 27
Table 8. Maximum Supply Currents
Power Supply Conditions
Maximum Current
Unit
Power Virus CoreMark
i.MX 6QuadPlus:
VDD_ARM_IN + VDD_ARM23_IN1
ARM frequency = 1200 MHz
ARM LDOs set to 1.3V
•T
j = 105°C
3920 2500 mA
ARM frequency = 996 MHz
ARM LDOs set to 1.3V
•T
j = 105°C
3730 2370 mA
i.MX 6DualPlus: VDD_ARM_IN2 ARM frequency = 1200 MHz
ARM LDOs set to 1.3V
•T
j = 105°C
2350 1200 mA
ARM frequency = 996 MHz
ARM LDOs set to 1.3V
•T
j = 105°C
2230 1140 mA
i.MX 6DualPlus: or i.MX 6Quad:
VDD_SOC_IN
Running 3DMark
GPU frequency = 720 MHz
SOC LDO set to 1.3V
•T
j = 105°C
3700 mA
VDD_HIGH_IN 1253 mA
VDD_SNVS_IN 2754 μA
USB_OTG_VBUS/
USB_H1_VBUS (LDO 3P0)
—25
5 mA
Primary Interface (IO) Supplies
NVCC_DRAM (see note6)
NVCC_ENET N=10 Use maximum IO equation7
NVCC_LCD N=29 Use maximum IO equation7
NVCC_GPIO N=24 Use maximum IO equation7
NVCC_CSI N=20 Use maximum IO equation7
NVCC_EIM0 N=19 Use maximum IO equation7
NVCC_EIM1 N=14 Use maximum IO equation7
NVCC_EIM2 N=20 Use maximum IO equation7
NVCC_JTAG N=6 Use maximum IO equation7
NVCC_RGMII N=6 Use maximum IO equation7
NVCC_SD1 N=6 Use maximum IO equation7
NVCC_SD2 N=6 Use maximum IO equation7
NVCC_SD3 N=11 Use maximum IO equation7
NVCC_NANDF N=26 Use maximum IO equation7
NVCC_MIPI 25.5 mA
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
28 NXP Semiconductors
Electrical Characteristics
4.1.6 Low Power Mode Supply Currents
Table 9 shows the current core consumption (not including I/O) of the i.MX 6DualPlus/6QuadPlus
processors in selected low power modes.
NVCC_LVDS2P5 NVCC_LVDS2P5 is connected to
VDD_HIGH_CAP at the board
level. VDD_HIGH_CAP is capable
of handing the current required by
NVCC_LVDS2P5.
MISC
DRAM_VREF 1 mA
1i.MX 6DualPlus numbers assume VDD_ARM23_IN and VDD_ARM23_CAP are connected to ground.
2i.MX 6DualPlus numbers assume VDD_ARM23_IN and VDD_ARM23_CAP are connected to ground.
3The actual maximum current drawn from VDD_HIGH_IN will be as shown plus any additional current drawn from the
VDD_HIGH_CAP outputs, depending upon actual application configuration (for example, NVCC_LVDS_2P5, NVCC_MIPI, or
HDMI, PCIe, and SATA VPH supplies).
4Under normal operating conditions, the maximum current on VDD_SNVS_IN is shown Table 8. The maximum VDD_SNVS_IN
current may be higher depending on specific operating configurations, such as BOOT_MODE[1:0] not equal to 00, or use of
the Tamper feature. During initial power on, VDD_SNVS_IN can draw up to 1 mA if the supply is capable of sourcing that
current. If less than 1 mA is available, the VDD_SNVS_CAP charge time will increase.
5This is the maximum current per active USB physical interface.
6The DRAM power consumption is dependent on several factors such as external signal termination. DRAM power calculators
are typically available from memory vendors which take into account factors such as signal termination.
See the i.MX 6Dual/6Quad Power Consumption Measurement Application Note (AN4509) for examples of DRAM power
consumption during specific use case scenarios.
7General equation for estimated, maximum power consumption of an IO power supply:
Imax = N x C x V x (0.5 x F)
Where:
N—Number of IO pins supplied by the power line
C—Equivalent external capacitive load
V—IO voltage
(0.5 xF)—Data change rate. Up to 0.5 of the clock rate (F)
In this equation, Imax is in Amps, C in Farads, V in Volts, and F in Hertz.
Table 9. Stop Mode Current and Power Consumption
Mode Test Conditions Supply Typical1Unit
WAIT Arm, SoC, and PU LDOs are set to 1.225 V
HIGH LDO set to 2.5 V
Clocks are gated
DDR is in self refresh
PLLs are active in bypass (24 MHz)
Supply voltages remain ON
VDD_ARM_IN (1.4 V) 6 mA
VDD_SOC_IN (1.4 V) 23 mA
VDD_HIGH_IN (3.0 V) 3.7 mA
Total 52 mW
Table 8. Maximum Supply Currents (continued)
Power Supply Conditions
Maximum Current
Unit
Power Virus CoreMark
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 29
STOP_ON Arm LDO set to 0.9 V
SoC and PU LDOs set to 1.225 V
HIGH LDO set to 2.5 V
PLLs disabled
DDR is in self refresh
VDD_ARM_IN (1.4 V) 7.5 mA
VDD_SOC_IN (1.4 V) 22 mA
VDD_HIGH_IN (3.0 V) 3.7 mA
Total 52 mW
STOP_OFF Arm LDO set to 0.9 V
SoC LDO set to 1.225 V
PU LDO is power gated
HIGH LDO set to 2.5 V
PLLs disabled
DDR is in self refresh
VDD_ARM_IN (1.4 V) 7.5 mA
VDD_SOC_IN (1.4 V) 13.5 mA
VDD_HIGH_IN (3.0 V) 3.7 mA
Total 41 mW
STANDBY ARM and PU LDOs are power gated
SoC LDO is in bypass
HIGH LDO is set to 2.5 V
PLLs are disabled
Low voltage
Well Bias ON
Crystal oscillator is enabled
VDD_ARM_IN (0.9 V) 0.1 mA
VDD_SOC_IN (1.05 V) 13 mA
VDD_HIGH_IN (3.0 V) 3.7 mA
Total 22 mW
Deep Sleep Mode
(DSM)
ARM and PU LDOs are power gated
SoC LDO is in bypass
HIGH LDO is set to 2.5 V
PLLs are disabled
Low voltage
Well Bias ON
Crystal oscillator and bandgap are disabled
VDD_ARM_IN (0.9 V) 0.1 mA
VDD_SOC_IN (1.05 V) 2 mA
VDD_HIGH_IN (3.0 V) 0.5 mA
Total 3.4 mW
SNVS Only VDD_SNVS_IN powered
All other supplies off
SRTC running
VDD_SNVS_IN (2.8V) 41 μA
Total 115 μW
1The typical values shown here are for information only and are not guaranteed. These values are average values measured
on a worst-case wafer at 25°C.
Table 9. Stop Mode Current and Power Consumption (continued)
Mode Test Conditions Supply Typical1Unit
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
30 NXP Semiconductors
Electrical Characteristics
4.1.7 USB PHY Current Consumption
4.1.7.1 Power Down Mode
In power down mode, everything is powered down, including the VBUS valid detectors, typical condition.
Table 10 shows the USB interface current consumption in power down mode.
NOTE
The currents on the VDD_HIGH_CAP and VDD_USB_CAP were
identified to be the voltage divider circuits in the USB-specific level shifters.
4.1.8 SATA Typical Power Consumption
Table 11 provides SATA PHY currents for certain Tx operating modes.
NOTE
Tx power consumption values are provided for a single transceiver. If
T = single transceiver power and C = Clock module power, the total power
required for N lanes = N x T + C.
Table 10. USB PHY Current Consumption in Power Down Mode
VDD_USB_CAP (3.0 V) VDD_HIGH_CAP (2.5 V) NVCC_PLL_OUT (1.1 V)
Current 5.1 μA1.7 μA <0.5 μA
Table 11. SATA PHY Current Drain
Mode Test Conditions Supply Typical Current Unit
P0: Full-power state1Single Transceiver SATA_VP 11 mA
SATA_VPH 13
Clock Module SATA_VP 6.9
SATA_VPH 6.2
P0: Mobile2Single Transceiver SATA_VP 11 mA
SATA_VPH 11
Clock Module SATA_VP 6.9
SATA_VPH 6.2
P0s: Transmitter idle Single Transceiver SATA_VP 9.4 mA
SATA_VPH 2.9
Clock Module SATA_VP 6.9
SATA_VPH 6.2
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 31
4.1.9 PCIe 2.0 Maximum Power Consumption
Table 12 provides PCIe PHY currents for certain operating modes.
P1: Transmitter idle, Rx powered
down, LOS disabled
Single Transceiver SATA_VP 0.67 mA
SATA_VPH 0.23
Clock Module SATA_VP 6.9
SATA_VPH 6.2
P2: Powered-down state, only
LOS and POR enabled
Single Transceiver SATA_VP 0.53 mA
SATA_VPH 0.11
Clock Module SATA_VP 0.036
SATA_VPH 0.12
PDDQ mode3Single Transceiver SATA_VP 0.13 mA
SATA_VPH 0.012
Clock Module SATA_VP 0.008
SATA_VPH 0.004
1Programmed for 1.0 V peak-to-peak Tx level.
2Programmed for 0.9 V peak-to-peak Tx level with no boost or attenuation.
3LOW power non-functional.
Table 12. PCIe PHY Current Drain
Mode Test Conditions Supply Max Current Unit
P0: Normal Operation 5G Operations PCIE_VP (1.1 V) 40 mA
PCIE_VPTX (1.1 V) 20
PCIE_VPH (2.5 V) 21
2.5G Operations PCIE_VP (1.1 V) 27
PCIE_VPTX (1.1 V) 20
PCIE_VPH (2.5 V) 20
P0s: Low Recovery Time
Latency, Power Saving State
5G Operations PCIE_VP (1.1 V) 30 mA
PCIE_VPTX (1.1 V) 2.4
PCIE_VPH (2.5 V) 18
2.5G Operations PCIE_VP (1.1 V) 20
PCIE_VPTX (1.1 V) 2.4
PCIE_VPH (2.5 V) 18
Table 11. SATA PHY Current Drain (continued)
Mode Test Conditions Supply Typical Current Unit
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
32 NXP Semiconductors
Electrical Characteristics
4.1.10 HDMI Maximum Power Consumption
Table 13 provides HDMI PHY currents for both Active 3D Tx with LFSR15 data pattern and Power-down
modes.
P1: Longer Recovery Time
Latency, Lower Power State
PCIE_VP (1.1 V) 12 mA
PCIE_VPTX (1.1 V) 2.4
PCIE_VPH (2.5 V) 12
Power Down PCIE_VP (1.1 V) 1.3 mA
PCIE_VPTX (1.1 V) 0.18
PCIE_VPH (2.5 V) 0.36
Table 13. HDMI PHY Current Drain
Mode Test Conditions Supply Max Current Unit
Active Bit rate 251.75 Mbps HDMI_VPH 14 mA
HDMI_VP 4.1 mA
Bit rate 279.27 Mbps HDMI_VPH 14 mA
HDMI_VP 4.2 mA
Bit rate 742.5 Mbps HDMI_VPH 17 mA
HDMI_VP 7.5 mA
Bit rate 1.485 Gbps HDMI_VPH 17 mA
HDMI_VP 12 mA
Bit rate 2.275 Gbps HDMI_VPH 16 mA
HDMI_VP 17 mA
Bit rate 2.97 Gbps HDMI_VPH 19 mA
HDMI_VP 22 mA
Power-down HDMI_VPH 49 μA
HDMI_VP 1100 μA
Table 12. PCIe PHY Current Drain (continued)
Mode Test Conditions Supply Max Current Unit
Electrical Characteristics
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
NXP Semiconductors 33
4.2 Power Supplies Requirements and Restrictions
The system design must comply with power-up sequence, power-down sequence, and steady state
guidelines as described in this section to ensure the reliable operation of the device. Any deviation from
these sequences may result in the following situations:
Excessive current during power-up phase
Prevention of the device from booting
Irreversible damage to the processor
4.2.1 Power-Up Sequence
For power-up sequence, the restrictions are as follows:
VDD_SNVS_IN supply must be turned ON before any other power supply. It may be connected
(shorted) with VDD_HIGH_IN supply.
If a coin cell is used to power VDD_SNVS_IN, then ensure that it is connected before any other
supply is switched on.
The SRC_POR_B signal controls the processor POR and must be immediately asserted at
power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP
supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no
restrictions.
NOTE
Ensure that there is no back voltage (leakage) from any supply on the board
towards the 3.3 V supply (for example, from the external components that
use both the 1.8 V and 3.3 V supplies).
NOTE
USB_OTG_VBUS and USB_H1_VBUS are not part of the power supply
sequence and can be powered at any time.
4.2.2 Power-Down Sequence
There are no special restrictions for i.MX 6DualPlus/6QuadPlus SoC.
4.2.3 Power Supplies Usage
All I/O pins must not be externally driven while the I/O power supply for the pin (NVCC_xxx) is
OFF. This can cause internal latch-up and malfunctions due to reverse current flows. For
information about I/O power supply of each pin, see the “Power Group” column of Table 96, “21
x 21 mm Functional Contact Assignments”.
When the SATA interface is not used, the SATA_VP and SATA_VPH supplies should be grounded.
The input and output supplies for rest of the ports (SATA_REXT, SATA_PHY_RX_N,
SATA_PHY_RX_P, and SATA_PHY_TX_N) can remain unconnected. It is recommended not to
turn OFF the SATA_VPH supply while the SATA_VP supply is ON, as it may lead to excessive
i.MX 6DualPlus/6QuadPlus Applications Processors Consumer Products, Rev. 3, 11/2018
34 NXP Semiconductors
Electrical Characteristics
power consumption. If boundary scan test is used, SATA_VP and SATA_VPH must remain
powered.
When the PCIE interface is not used, the PCIE_VP, PCIE_VPH, and PCIE_VPTX supplies should
be grounded. The input and output supplies for rest of the ports (PCIE_REXT, PCIE_RX_N,
PCIE_RX_P, PCIE_TX_N, and PCIE_TX_P) can remain unconnected. It is recommended not to
turn the PCIE_VPH supply OFF while the PCIE_VP supply is ON, as it may lead to excessive
power consumption. If boundary scan test is used, PCIE_VP, PCIE_VPH, and PCIE_VPTX must
remain powered.
4.3 Integrated LDO Voltage Regulator Parameters
Various internal supplies can be powered ON from internal LDO voltage regulators. All the supply pins
named *_CAP must be connected to external capacitors. The onboard LDOs are intended for internal use
only and should not be used to power any external circuitry. See the i.MX 6DualPlus/6QuadPlus reference
manual (IMX6DQPRM) for details on the power tree scheme recommended operation.
NOTE
The *_CAP signals should not be powered externally. These signals are
intended for internal LDO or LDO bypass operation only.
4.3.1 Digital Regulators (LDO_ARM, LDO_PU, LDO_SOC)
There are three digital LDO regulators (“Digital”, because of the logic loads that they drive, not because
of their construction). The advantages of the regulators are to reduce the input supply variation because of
their input supply ripple rejection and their on die trimming. This translates into more voltage for the die
producing higher operating frequencies. These regulators have three basic modes.
Bypass. The regulation FET is switched fully on passing the external voltage, DCDC_LOW, to the
load unaltered. The analog part of the regulator is powered down in this state, removing any loss
other than the IR drop through the power grid and FET.
Power Gate. The regulation FET is switched fully off limiting the current draw from the supply.
The analog part of the regulator is powered down here limiting the power consumption.
Analog regulation mode. The regulation FET is controlled such that the output voltage of the
regulator equals the programmed target voltage. The target voltage is fully programmable in 25 mV
steps.
Optionally LDO_SOC/VDD_SOC_CAP can be used to power the HDMI, PCIe, and SATA PHY's through
external connections.
For additional information, see the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM).
4.3.2 Regulators for Analog Modules
4.3.2.1 LDO_1P1 / NVCC_PLL_OUT
The LDO_1P1 regulator implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 6 for minimum and maximum input requirements). Typical Programming Operating Range is 1.0 V
Electrical Characteristics
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to 1.2 V with the nominal default setting as 1.1 V. The LDO_1P1 supplies the 24 MHz oscillator, PLLs,
and USB PHY. A programmable brown-out detector is included in the regulator that can be used by the
system to determine when the load capability of the regulator is being exceeded to take the necessary steps.
Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.
Active-pull-down can also be enabled for systems requiring this feature.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors
(IMX6DQ6SDLHDG).
For additional information, see the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM).
4.3.2.2 LDO_2P5 / VDDHIGH_CAP
The LDO_2P5 module implements a programmable linear-regulator function from VDD_HIGH_IN (see
Table 6 for min and max input requirements). Typical Programming Operating Range is 2.25 V to 2.75 V
with the nominal default setting as 2.5 V. The LDO_2P5 supplies the eFuses, PLLs, and USB PHY.
Optionally it can be used to supply the HDMI, LVDS, MIPI, PCIe, and SATA PHY's through external
connections. A programmable brown-out detector is included in the regulator that can be used by the
system to determine when the load capability of the regulator is being exceeded, to take the necessary
steps. Current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed.
Active-pull-down can also be enabled for systems requiring this feature. An alternate self-biased
low-precision weak-regulator is included that can be enabled for applications needing to keep the output
voltage alive during low-power modes where the main regulator driver and its associated global bandgap
reference module are disabled. The output of the weak-regulator is not programmable and is a function of
the input supply as well as the load current. Typically, with a 3 V input supply the weak-regulator output
is 2.525 V and its output impedance is approximately 40 Ω.
For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors
(IMX6DQ6SDLHDG).
For additional information, see the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM).
4.3.2.3 LDO_USB / VDD_VBUS_CAP
The LDO_USB module implements a programmable linear-regulator function from the
USB_OTG_VBUS and USB_H1_VBUS voltages (4.4 V–5.25 V) to produce a nominal 3.0 V output
voltage. A programmable brown-out detector is included in the regulator that can be used by the system to
determine when the load capability of the regulator is being exceeded, to take the necessary steps. This
regulator has a built in power-mux that allows the user to select to run the regulator from either VBUS
supply, when both are present. If only one of the VBUS voltages is present, then the regulator
automatically selects this supply. Current limit is also included to help the system meet in-rush current
targets. If no VBUS voltage is present, then the VBUSVALID threshold setting will prevent the regulator
from being enabled.
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For information on external capacitor requirements for this regulator, see the Hardware Development
Guide for i.MX 6Quad, 6Dual, 6DualLite, 6Solo Families of Applications Processors
(IMX6DQ6SDLHDG).
For additional information, see the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM).
4.4 PLL Electrical Characteristics
4.4.1 Audio/Video PLL Electrical Parameters
4.4.2 528 MHz PLL
4.4.3 Ethernet PLL
Table 14. Audio/Video PLL Electrical Parameters
Parameter Value
Clock output range 650 MHz ~1.3 GHz
Reference clock 24 MHz
Lock time <11250 reference cycles
Table 15. 528 MHz PLL Electrical Parameters
Parameter Value
Clock output range 528 MHz PLL output
Reference clock 24 MHz
Lock time <11250 reference cycles
Table 16. Ethernet PLL Electrical Parameters
Parameter Value
Clock output range 500 MHz
Reference clock 24 MHz
Lock time <11250 reference cycles
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4.4.4 480 MHz PLL
4.4.5 MLB PLL
The MediaLB PLL is necessary in the MediaLB 6-Pin implementation to phase align the internal and
external clock edges, effectively tuning out the delay of the differential clock receiver and is also
responsible for generating the higher speed internal clock, when the internal-to-external clock ratio is
not 1:1.
4.4.6 Arm PLL
4.5 On-Chip Oscillators
4.5.1 OSC24M
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implements an oscillator. The oscillator is powered from NVCC_PLL_OUT.
The system crystal oscillator consists of a Pierce-type structure running off the digital supply. A straight
forward biased-inverter implementation is used.
4.5.2 OSC32K
This block implements an amplifier that when combined with a suitable quartz crystal and external load
capacitors implements a low power oscillator. It also implements a power mux such that it can be powered
Table 17. 480 MHz PLL Electrical Parameters
Parameter Value
Clock output range 480 MHz PLL output
Reference clock 24 MHz
Lock time <383 reference cycles
Table 18. MLB PLL Electrical Parameters
Parameter Value
Lock time <1.5 ms
Table 19. Arm PLL Electrical Parameters
Parameter Value
Clock output range 650 MHz~1.3 GHz
Reference clock 24 MHz
Lock time <2250 reference cycles
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from either a ~3 V backup battery (VDD_SNVS_IN) or VDD_HIGH_IN such as the oscillator consumes
power from VDD_HIGH_IN when that supply is available and transitions to the back up battery when
VDD_HIGH_IN is lost.
In addition, if the clock monitor determines that the OSC32K is not present, then the source of the 32 kHz
clock will automatically switch to the internal ring oscillator.
CAUTION
The internal RTC oscillator does not provide an accurate frequency and is
affected by process, voltage, and temperature variations. NXP strongly
recommends using an external crystal as the RTC_XTALI reference. If the
internal oscillator is used instead, careful consideration must be given to the
timing implications on all of the SoC modules dependent on this clock.
The OSC32k runs from VDD_SNVS_CAP, which comes from the VDD_HIGH_IN/VDD_SNVS_IN
power mux.
4.6 I/O DC Parameters
This section includes the DC parameters of the following I/O types:
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes
•LVDS I/O
•MLB I/O
Table 20. OSC32K Main Characteristics
Parameter Min Typ Max Comments
Fosc 32.768 kHz This frequency is nominal and determined mainly by the crystal selected. 32.0 K
would work as well.
Current
consumption
—4 μA The typical value shown is only for the oscillator, driven by an external crystal.
If the internal ring oscillator is used instead of an external crystal, then
approximately 25 μA must be added to this value.
Bias resistor 14 MΩ This the integrated bias resistor that sets the amplifier into a high gain state. Any
leakage through the ESD network, external board leakage, or even a scope probe
that is significant relative to this value will debias the amplifier. The debiasing will
result in low gain, and will impact the circuit's ability to start up and maintain
oscillations.
Target Crystal Properties
Cload 10 pF Usually crystals can be purchased tuned for different Cloads. This Cload value is
typically 1/2 of the capacitances realized on the PCB on either side of the quartz.
A higher Cload will decrease oscillation margin, but increases current oscillating
through the crystal.
ESR 50 kΩ100 kΩEquivalent series resistance of the crystal. Choosing a crystal with a higher value
will decrease the oscillating margin.
E E +'
Electrical Characteristics
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NOTE
The term ‘OVDD’ in this section refers to the associated supply rail of an
input or output.
Figure 3. Circuit for Parameters Voh and Vol for I/O Cells
4.6.1 XTALI and RTC_XTALI (Clock Inputs) DC Parameters
Table 21 shows the DC parameters for the clock inputs.
NOTE
The Vil and Vih specifications only apply when an external clock source is
used. If a crystal is used, Vil and Vih do not apply.
4.6.2 General Purpose I/O (GPIO) DC Parameters
Table 22 shows DC parameters for GPIO pads. The parameters in Table 22 are guaranteed per the
operating ranges in Table 6, unless otherwise noted.
Table 21. XTALI and RTC_XTALI DC Parameters
Parameter Symbol Test Conditions Min Typ Max Unit
XTALI high-level DC input voltage Vih 0.8 x NVCC_PLL_OUT NVCC_PLL_ OUT V
XTALI low-level DC input voltage Vil 0 0.2 V
RTC_XTALI high-level DC input
voltage
Vih 0.8 — 1.1(See note 1)
1This voltage specification must not be exceeded and, as such, is an absolute maximum specification.
V
RTC_XTALI low-level DC input
voltage
Vil 0 — 0.2 V
Input capacitance CIN Simulated data 5 pF
XTALI input leakage current at
startup
IXTALI_STARTUP Power-on startup for
0.15 msec with a driven
24 MHz clock
at 1.1 V. 2
2This current draw is present even if an external clock source directly drives XTALI.
— 600 μA
DC input current IXTALI_DC ——2.5μA
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4.6.3 DDR I/O DC Parameters
The DDR I/O pads support LPDDR2 and DDR3/DDR3L operational modes.
To date LPDDR2 has not been fully validated or supported in the BSP. For further details contact your local
NXP representative.
Table 22. GPIO I/O DC Parameters
Parameter Symbol Test Conditions Min Max Unit
High-level output voltage1
1Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6 V,
and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must be
controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods.
Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
Voh Ioh = -0.1 mA (DSE2 = 001, 010)
Ioh = -1 mA
(DSE = 011, 100, 101, 110, 111)
2DSE is the Drive Strength Field setting in the associated IOMUX control register.
OVDD – 0.15 V
Low-level output voltage1Vol Iol = 0.1 mA (DSE2 = 001, 010)
Iol = 1mA
(DSE = 011, 100, 101, 110, 111)
—0.15V
High-Level DC input voltage1, 3
3To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
Vih 0.7 ×OVDD OVDD V
Low-Level DC input voltage1, 3Vil 0 0.3 ×OVDD V
Input Hysteresis Vhys OVDD = 1.8 V
OVDD = 3.3 V
0.25 — V
Schmitt trigger VT+3, 4
4Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled.
VT+ 0.5 ×OVDD — V
Schmitt trigger VT–3, 4 VT– 0.5 ×OVDD V
Input current (no pull-up/down) Iin Vin = OVDD or 0 -1 1 μA
Input current (22 kΩ pull-up) Iin Vin = 0 V
Vin = OVDD
—212
1μA
Input current (47 kΩ pull-up) Iin Vin = 0 V
Vin = OVDD
—100
1μA
Input current (100 kΩ pull-up) Iin Vin = 0 V
Vin= OVDD
—48
1μA
Input current (100 kΩ pull-down) Iin Vin = 0 V
Vin = OVDD
—1
48 μA
Keeper circuit resistance Rkeep Vin = 0.3 x OVDD
Vin = 0.7 x OVDD
105 175 kΩ
Electrical Characteristics
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4.6.4 RGMII I/O 2.5V I/O DC Electrical Parameters
The RGMII interface complies with the RGMII standard version 1.3. The parameters in Table 23 are
guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 23. RGMII I/O 2.5V I/O DC Electrical Parameters1
1 Input Mode Selection: SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 10 (1.8V Mode)
SW_PAD_CTL_GRP_DDR_TYPE_RGMII = 11 (2.5V Mode).
Parameter Symbol Test Conditions Min Max Units
High-level output voltage1VOH Ioh= -0.1 mA (DSE=001,010)
Ioh= -1.0 mA (DSE=011,100,101,110,111)
OVDD-0.15 —V
Low-level output voltage1VOL Iol= 0.1 mA (DSE=001,010)
Iol= 1.0 mA (DSE=011,100,101,110,111)
—0.15V
Input Reference Voltage Vref 0.49xOVDD 0.51xOVDD V
High-Level input voltage 2, 3
2Overshoot and undershoot conditions (transitions above OVDD and below GND) on switching pads must be held below 0.6
V, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. Overshoot/ undershoot must
be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other
methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device.
3To maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current DC
level through to the target DC level, Vil or Vih. Monotonic input transition time is from 0.1 ns to 1 s.
VIH 0.7xOVDD OVDD V
Low-Level input voltage 2, 3 VIL —0
0.3xOVDD V
Input Hysteresis(OVDD=1.8V) VHYS_HighVDD OVDD=1.8V 250 — mV
Input Hysteresis(OVDD=2.5V) VHYS_HighVDD OVDD=2.5V 250 — mV
Schmitt trigger VT+ 3, 4
4Hysteresis of 250 mV is guaranteed over all operating conditions when hysteresis is enabled
(register IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC[HYS]= 0).
VTH+ —0.5xOVDDmV
Schmitt trigger VT- 3, 4VTH- 0.5xOVDD mV
Pull-up resistor (22 kΩ PU) RPU_22K Vin=0V 212 μA
Pull-up resistor (22 kΩ PU) RPU_22K Vin=OVDD 1 μA
Pull-up resistor (47 kΩ PU) RPU_47K Vin=0V 100 μA
Pull-up resistor (47 kΩ PU) RPU_47K Vin=OVDD 1 μA
Pull-up resistor (100 kΩ PU) RPU_100K Vin=0V 48 μA
Pull-up resistor (100 kΩ PU) RPU_100K Vin=OVDD 1 μA
Pull-down resistor (100 kΩ PD) RPD_100K Vin=OVDD 48 μA
Pull-down resistor (100 kΩ PD) RPD_100K Vin=0V 1 μA
Keeper Circuit Resistance Rkeep 105 165 kΩ
Input current (no pull-up/down) Iin VI = 0,VI = OVDD -2.9 2.9 μA
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4.6.4.1 LPDDR2 Mode I/O DC Parameters
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported
DDR3/DDR3L/LPDDR2 Configurations.”
The parameters in Table 24 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
4.6.4.2 DDR3/DDR3L Mode I/O DC Parameters
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported
DDR3/DDR3L/LPDDR2 Configurations.”
The parameters in Table 25 are guaranteed per the operating ranges in Table 6, unless otherwise noted.
Table 24. LPDDR2 I/O DC Electrical Parameters1
1Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Parameters Symbol Test Conditions Min Max Unit
High-level output voltage Voh Ioh = -0.1 mA 0.9 ×OVDD — V
Low-level output voltage Vol Iol = 0.1 mA 0.1 ×OVDD V
Input reference voltage Vref 0.49 ×OVDD 0.51 ×OVDD
DC input High Voltage Vih(dc) Vref+0.13V OVDD V
DC input Low Voltage Vil(dc) OVSS Vref-0.13V V
Differential Input Logic High Vih(diff) 0.26 See Note 2
2The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot (see Table 30).
Differential Input Logic Low Vil(diff) See Note 2-0.26 —
Input current (no pull-up/down) Iin Vin = 0 or OVDD -2.5 2.5 μA
Pull-up/pull-down impedance mismatch MMpupd -15 +15 %
240 Ω unit calibration resolution Rres 10 Ω
Keeper circuit resistance Rkeep 110 175 kΩ
Table 25. DDR3/DDR3L I/O DC Electrical Parameters
Parameters Symbol Test Conditions Min Max Unit
High-level output voltage
Voh
Ioh = -0.1 mA
Voh (DSE = 001)
0.8 ×OVDD1—V
Ioh = -1 mA
Voh (for all except DSE = 001)
Low-level output voltage
Vol
Iol = 0.1 mA
Vol (DSE = 001)
—0.2×OVDD V
Iol = 1 mA
Vol (for all except DSE = 001)
Input reference voltage Vref2—0.49×OVDD 0.51 ×OVDD
Electrical Characteristics
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4.6.5 LVDS I/O DC Parameters
The LVDS interface complies with TIA/EIA 644-A standard. See TIA/EIA STANDARD 644-A,
Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
Table 26 shows the Low Voltage Differential Signaling (LVDS) I/O DC parameters.
4.6.6 MLB 6-Pin I/O DC Parameters
The MLB interface complies with Analog Interface of 6-pin differential Media Local Bus specification
version 4.1. See 6-pin differential MLB specification v4.1, “MediaLB 6-pin interface Electrical
Characteristics” for details.
NOTE
The MLB 6-pin interface does not support speed mode 8192fs.
Table 27 shows the Media Local Bus (MLB) I/O DC parameters.
DC input Logic High Vih(dc) Vref+0.1 OVDD V
DC input Logic Low Vil(dc) OVSS Vref-0.1 V
Differential input Logic High Vih(diff) 0.2 See Note3V
Differential input Logic Low Vil(diff) See Note3-0.2 V
Termination Voltage Vtt Vtt tracking OVDD/2 0.49 ×OVDD 0.51 ×OVDD V
Input current (no pull-up/down) Iin Vin = 0 or OVDD -2.9 2.9 μA
Pull-up/pull-down impedance mismatch MMpupd —-1010%
240 Ω unit calibration resolution Rres 10 Ω
Keeper circuit resistance Rkeep 105 175 kΩ
1OVDD – I/O power supply (1.425 V–1.575 V for DDR3 and 1.283 V–1.45 V for DDR3L).
2Vref – DDR3/DDR3L external reference voltage.
3The single-ended signals need to be within the respective limits (Vih(dc) max, Vil(dc) min) for single-ended signals as well as
the limitations for overshoot and undershoot (see Table 31).
Table 26. LVDS I/O DC Parameters
Parameter Symbol Test Conditions Min Max Unit
Output Differential Voltage VOD Rload=100 Ω between padP and padN 250 450 mV
Output High Voltage VOH IOH = 0 mA 1.25 1.6
VOutput Low Voltage VOL IOL = 0 mA 0.9 1.25
Offset Voltage VOS 1.125 1.375
Table 25. DDR3/DDR3L I/O DC Electrical Parameters (continued)
Parameters Symbol Test Conditions Min Max Unit
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4.7 I/O AC Parameters
This section includes the AC parameters of the following I/O types:
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2 and DDR3/DDR3L modes
•LVDS I/O
•MLB I/O
The GPIO and DDR I/O load circuit and output transition time waveforms are shown in Figure 4 and
Figure 5.
Figure 4. Load Circuit for Output
Figure 5. Output Transition Time Waveform
Table 27. MLB I/O DC Parameters
Parameter Symbol Test Conditions Min Max Unit
Output Differential Voltage VOD Rload = 50 Ω between padP and padN 300 500 mV
Output High Voltage VOH 1.15 1.75 V
Output Low Voltage VOL 0.75 1.35 V
Common-mode Output Voltage
((Vpad_P + Vpad_N) / 2))
VOCM 11.5
V
Differential Output Impedance ZO—1.6kΩ
Test Point
From Output
CL
CL includes package, probe and fixture capacitance
Under Test
0V
OVDD
20%
80% 80%
20%
tr tf
Output (at pad)
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4.7.1 General Purpose I/O AC Parameters
The I/O AC parameters for GPIO in slow and fast modes are presented in the Table 28 and Table 29,
respectively. Note that the fast or slow I/O behavior is determined by the appropriate control bits in the
IOMUXC control registers.
Table 28. General Purpose I/O AC Parameters 1.8 V Mode
Parameter Symbol Test Condition Min Typ Max Unit
Output Pad Transition Times, rise/fall
(Max Drive, DSE=111)
tr, tf 15 pF Cload, slow slew rate
15 pF Cload, fast slew rate —— 2.72/2.79
1.51/1.54
ns
Output Pad Transition Times, rise/fall
(High Drive, DSE=101)
tr, tf 15 pF Cload, slow slew rate
15 pF Cload, fast slew rate —— 3.20/3.36
1.96/2.07
Output Pad Transition Times, rise/fall
(Medium Drive, DSE=100)
tr, tf 15 pF Cload, slow slew rate
15 pF Cload, fast slew rate —— 3.64/3.88
2.27/2.53
Output Pad Transition Times, rise/fall
(Low Drive. DSE=011)
tr, tf 15 pF Cload, slow slew rate
15 pF Cload, fast slew rate —— 4.32/4.50
3.16/3.17
Input Transition Times1
1Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
trm — — 25 ns
Table 29. General Purpose I/O AC Parameters 3.3 V Mode
Parameter Symbol Test Condition Min Typ Max Unit
Output Pad Transition Times, rise/fall
(Max Drive, DSE=101)
tr, tf 15 pF Cload, slow slew rate
15 pF Cload, fast slew rate —— 1.70/1.79
1.06/1.15
ns
Output Pad Transition Times, rise/fall
(High Drive, DSE=011)
tr, tf 15 pF Cload, slow slew rate
15 pF Cload, fast slew rate —— 2.35/2.43
1.74/1.77
Output Pad Transition Times, rise/fall
(Medium Drive, DSE=010)
tr, tf 15 pF Cload, slow slew rate
15 pF Cload, fast slew rate —— 3.13/3.29
2.46/2.60
Output Pad Transition Times, rise/fall
(Low Drive. DSE=001)
tr, tf 15 pF Cload, slow slew rate
15 pF Cload, fast slew rate —— 5.14/5.57
4.77/5.15
Input Transition Times1
1Hysteresis mode is recommended for inputs with transition times greater than 25 ns.
trm — — 25 ns
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4.7.2 DDR I/O AC Parameters
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported
DDR3/DDR3L/LPDDR2 Configurations.”
Table 30 shows the AC parameters for DDR I/O operating in LPDDR2 mode.
Table 31 shows the AC parameters for DDR I/O operating in DDR3/DDR3L mode.
Table 30. DDR I/O LPDDR2 Mode AC Parameters1
1Note that the JEDEC LPDDR2 specification (JESD209_2B) supersedes any specification in this document.
Parameter Symbol Test Condition Min Typ Max Unit
AC input logic high Vih(ac) Vref + 0.22 OVDD V
AC input logic low Vil(ac) 0 Vref – 0.22 V
AC differential input high voltage2
2Vid(ac) specifies the input differential voltage |Vtr Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) Vil(ac).
Vidh(ac) 0.44 — V
AC differential input low voltage Vidl(ac) 0.44 V
Input AC differential cross point voltage3
3The typical value of Vix(ac) is expected to be about 0.5 ×OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Vix(ac) Relative to Vref -0.12 0.12 V
Over/undershoot peak Vpeak 0.35 V
Over/undershoot area (above OVDD
or below OVSS)
Varea 400 MHz 0.2 V-ns
Single output slew rate, measured
between Vol(ac) and Voh(ac)
tsr 50 Ω to Vref.
5 pF load.
Drive impedance = 4 0 Ω ±30%
1.5 3.5 V/ns
50 Ω to Vref.
5pF load.
Drive impedance = 60 Ω ±30%
1—2.5
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD clk = 400 MHz ——
0.1 ns
Table 31. DDR I/O DDR3/DDR3L Mode AC Parameters1
Parameter Symbol Test Condition Min Typ Max Unit
AC input logic high Vih(ac) Vref + 0.175 OVDD V
AC input logic low Vil(ac) 0 Vref – 0.175 V
AC differential input voltage2Vid(ac) 0.35 — V
Input AC differential cross point voltage3Vix(ac) Relative to Vref Vref – 0.15 Vref + 0.15 V
Over/undershoot peak Vpeak 0.4 V
Over/undershoot area (above OVDD
or below OVSS)
Varea 533 MHz 0.5 V-ns
V (Difierenlia‘) 0V 0V VDIFF = {padp} , (padn) 0V 20%
Electrical Characteristics
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4.7.3 LVDS I/O AC Parameters
The differential output transition time waveform is shown in Figure 6.
Figure 6. Differential LVDS Driver Transition Time Waveform
Table 32 shows the AC parameters for LVDS I/O.
4.7.4 MLB 6-Pin I/O AC Parameters
The differential output transition time waveform is shown in Figure 7.
Single output slew rate, measured between
Vol(ac) and Voh(ac)
tsr Driver impedance =
34 Ω
2.5 — 5 V/ns
Skew between pad rise/fall asymmetry +
skew caused by SSN
tSKD clk = 533 MHz ——
0.1 ns
1Note that the JEDEC JESD79_3C specification supersedes any specification in this document.
2Vid(ac) specifies the input differential voltage |Vtr-Vcp| required for switching, where Vtr is the “true” input signal and Vcp is
the “complementary” input signal. The Minimum value is equal to Vih(ac) – Vil(ac).
3The typical value of Vix(ac) is expected to be about 0.5 ×OVDD. and Vix(ac) is expected to track variation of OVDD. Vix(ac)
indicates the voltage at which differential input signal must cross.
Table 32. I/O AC Parameters of LVDS Pad
Parameter Symbol Test Condition Min Typ Max Unit
Differential pulse skew1
1tSKD = | tPHLD –t
PLHD |, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
tSKD
Rload = 100 Ω,
Cload = 2 pF
— 0.25
nsTransition Low to High Time2
2Measurement levels are 20–80% from output voltage.
tTLH ——0.5
Transition High to Low Time2tTHL ——0.5
Operating Frequency f 600 800 MHz
Offset voltage imbalance Vos 150 mV
Table 31. DDR I/O DDR3/DDR3L Mode AC Parameters1 (continued)
Parameter Symbol Test Condition Min Typ Max Unit
padp
padn
VDIFF
0V (Differential)
VDIFF = {padp} - {padn}
tTLH
20%
80%
20%
80%
tTHL
VOH
VOL
0V
0V
0V
0V (Differential) 0V 0V VDIFF = (padp) - 0V (”ad") 20% . MLE raw map: ”AU M (19.4 MLB PHV Ipp_do_d ,, in 0 F D o 4&9‘0;D (:7 > mp_one_s 7 pad"; IDprI (1 Plan.“ 7 D o B D a IDD_c\K_In_(x N ‘ Ipp_clk_ln_rx , signal/Dang nansmmu Swgnalle receiver mm W and samphng FF: and sampllng FF: DIUREI 'P L own ‘ J cm. 2 J‘ om“ - 0m“ ‘
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Electrical Characteristics
Figure 7. Differential MLB Driver Transition Time Waveform
A 4-stage pipeline is used in the MLB 6-pin implementation to facilitate design, maximize throughput, and
allow for reasonable PCB trace lengths. Each cycle is one ipp_clk_in* (internal clock from MLB PLL)
clock period. Cycles 2, 3, and 4 are MLB PHY related. Cycle 2 includes clock-to-output delay of
Signal/Data sampling flip-flop and Transmitter, Cycle 3 includes clock-to-output delay of Signal/Data
clocked receiver, Cycle 4 includes clock-to-output delay of Signal/Data sampling flip-flop.
MLB 6-pin pipeline diagram is shown in Figure 8.
Figure 8. MLB 6-Pin Pipeline Diagram
Table 33 shows the AC parameters for MLB I/O.
Table 33. I/O AC Parameters of MLB PHY
Parameter Symbol Test Condition Min Typ Max Unit
Differential pulse skew1
1tSKD = | tPHLD –t
PLHD |, is the magnitude difference in differential propagation delay time between the positive going edge and
the negative going edge of the same channel.
tSKD Rload = 50 Ω
between padP
and padN
—— 0.1
nsTransition Low to High Time2
2Measurement levels are 20-80% from output voltage.
tTLH —— 1
Transition High to Low Time tTHL —— 1
MLB external clock Operating Frequency fclk_ext 102.4 MHz
MLB PLL clock Operating Frequency fclk_pll 307.2 MHz
padp
padn
VDIFF
0V (Differential)
VDIFF = {padp} - {padn}
tTLH
20%
80%
20%
80%
tTHL
VOH
VOL
0V
0V
0V
Electrical Characteristics
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NXP Semiconductors 49
4.8 Output Buffer Impedance Parameters
This section defines the I/O impedance parameters of the i.MX 6DualPlus/6QuadPlus processors for the
following I/O types:
General Purpose I/O (GPIO)
Double Data Rate I/O (DDR) for LPDDR2, and DDR3 modes
•LVDS I/O
•MLB I/O
NOTE
GPIO and DDR I/O output driver impedance is measured with “long”
transmission line of impedance Ztl attached to I/O pad and incident wave
launched into transmission line. Rpu/Rpd and Ztl form a voltage divider that
defines specific voltage of incident wave relative to OVDD. Output driver
impedance is calculated from this voltage divider (see Figure 9).
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Electrical Characteristics
Figure 9. Impedance Matching Load for Measurement
ipp_do
Cload = 1p
Ztl Ω, L = 20 inches
predriver
PMOS (Rpu)
NMOS (Rpd)
pad
OVDD
OVSS
t,(ns)
U,(V)
OVDD
t,(ns)
0
VDD
Vin (do)
Vout (pad)
U,(V)
Vref
Rpu =
Vovdd–Vref1
Vref1
× Ztl
Rpd = × Ztl
Vref2
Vovdd–Vref2
Vref1 Vref2
0
Electrical Characteristics
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NXP Semiconductors 51
4.8.1 GPIO Output Buffer Impedance
Table 34 shows the GPIO output buffer impedance (OVDD 1.8 V).
Table 35 shows the GPIO output buffer impedance (OVDD 3.3 V).
Table 34. GPIO Output Buffer Average Impedance (OVDD 1.8 V)
Parameter Symbol Drive Strength (DSE) Typ Value Unit
Output Driver
Impedance Rdrv
001
010
011
100
101
110
111
260
130
90
60
50
40
33
Ω
Table 35. GPIO Output Buffer Average Impedance (OVDD 3.3 V)
Parameter Symbol Drive Strength (DSE) Typ Value Unit
Output Driver
Impedance Rdrv
001
010
011
100
101
110
111
150
75
50
37
30
25
20
Ω
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Electrical Characteristics
4.8.2 DDR I/O Output Buffer Impedance
For details on supported DDR memory configurations, see Section 4.10.2, “MMDC Supported
DDR3/DDR3L/LPDDR2 Configurations.”
Table 36 shows DDR I/O output buffer impedance of i.MX 6DualPlus/6QuadPlus processors.
Note:
1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.
2. Calibration is done against 240 W external reference resistor.
3. Output driver impedance deviation (calibration accuracy) is ±5% (max/min impedance) across PVTs.
4.8.3 LVDS I/O Output Buffer Impedance
The LVDS interface complies with TIA/EIA 644-A standard. See, TIA/EIA STANDARD 644-A,
“Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits” for details.
4.8.4 MLB 6-Pin I/O Differential Output Impedance
Table 37 shows MLB 6-pin I/O differential output impedance of i.MX 6DualPlus/6QuadPlus processors.
Table 36. DDR I/O Output Buffer Impedance
Parameter Symbol Test Conditions
Typical
Unit
NVCC_DRAM=1.5 V
(DDR3)
DDR_SEL=11
NVCC_DRAM=1.2 V
(LPDDR2)
DDR_SEL=10
Output Driver
Impedance Rdrv
Drive Strength (DSE) =
000
001
010
011
100
101
110
111
Hi-Z
240
120
80
60
48
40
34
Hi-Z
240
120
80
60
48
40
34
Ω
Table 37. MLB 6-Pin I/O Differential Output Impedance
Parameter Symbol Test Conditions Min Typ Max Unit
Differential Output Impedance ZO—1.6kΩ
Electrical Characteristics
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4.9 System Modules Timing
This section contains the timing and electrical parameters for the modules in each i.MX
6DualPlus/6QuadPlus processor.
4.9.1 Reset Timing Parameters
Figure 10 shows the reset timing and Table 38 lists the timing parameters.
Figure 10. Reset Timing Diagram
4.9.2 WDOG Reset Timing Parameters
Figure 11 shows the WDOG reset timing and Table 39 lists the timing parameters.
Figure 11. WDOG1_B Timing Diagram
NOTE
XTALOSC_RTC_XTALI is approximately 32 kHz.
XTALOSC_RTC_XTALI cycle is one period or approximately 30 μs.
NOTE
WDOG1_B output signals (for each one of the Watchdog modules) do not
have dedicated pins, but are muxed out through the IOMUX. See the IOMUX
manual for detailed information.
Table 38. Reset Timing Parameters
ID Parameter Min Max Unit
CC1 Duration of SRC_POR_B to be qualified as valid 1 XTALOSC_RTC_ XTALI cycle
Table 39. WDOG1_B Timing Parameters
ID Parameter Min Max Unit
CC3 Duration of WDOG1_B Assertion 1 XTALOSC_RTC_ XTALI cycle
SRC_POR_B
CC1
(Input)
WDOG1_B
CC3
(Output)
DATA
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Electrical Characteristics
4.9.3 External Interface Module (EIM)
The following subsections provide information on the EIM. Maximum operating frequency for EIM data
transfer is 104 MHz. Timing parameters in this section that are given as a function of register settings or
clock periods are valid for the entire range of allowed frequencies (0–104 MHz).
4.9.3.1 EIM Interface Pads Allocation
EIM supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes.
Table 40 provides EIM interface pads allocation in different modes.
Table 40. EIM Internal Module Multiplexing1
1For more information on configuration ports mentioned in this table, see the i.MX 6DualPlus/6QuadPlus reference manual
(IMX6DQPRM).
Setup
Non Multiplexed Address/Data Mode Multiplexed
Address/Data mode
8 Bit 16 Bit 32 Bit 16 Bit 32 Bit
MUM = 0,
DSZ = 100
MUM = 0,
DSZ = 101
MUM = 0,
DSZ = 110
MUM = 0,
DSZ = 111
MUM = 0,
DSZ = 001
MUM = 0,
DSZ = 010
MUM = 0,
DSZ = 011
MUM = 1,
DSZ = 001
MUM = 1,
DSZ = 011
EIM_ADDR
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_AD
[15:00]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_ADDR
[25:16]
EIM_DATA
[09:00]
EIM_DATA
[07:00],
EIM_EB0_B
EIM_DATA
[07:00]
———EIM_DATA
[07:00]
—EIM_DATA
[07:00]
EIM_AD
[07:00]
EIM_AD
[07:00]
EIM_DATA
[15:08],
EIM_EB1_B
—EIM_DATA
[15:08]
——EIM_DATA
[15:08]
—EIM_DATA
[15:08]
EIM_AD
[15:08]
EIM_AD
[15:08]
EIM_DATA
[23:16],
EIM_EB2_B
——EIM_DATA
[23:16]
——EIM_DATA
[23:16]
EIM_DATA
[23:16]
—EIM_DATA
[07:00]
EIM_DATA
[31:24],
EIM_EB3_B
———EIM_DATA
[31:24]
EIM_DATA
[31:24]
EIM_DATA
[31:24]
—EIM_DATA
[15:08]
Electrical Characteristics
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4.9.3.2 General EIM Timing-Synchronous Mode
Figure 12, Figure 13, and Table 41 specify the timings related to the EIM module. All EIM output control
signals may be asserted and deasserted by an internal clock synchronized to the EIM_BCLK rising edge
according to corresponding assertion/negation control fields.
Figure 12. EIM Output Timing Diagram
Figure 13. EIM Input Timing Diagram
4.9.3.3 Examples of EIM Synchronous Accesses
Table 41. EIM Bus Timing Parameters
ID Parameter Min1Max1Unit
WE1 EIM_BCLK cycle time2t×(k+1) — ns
WE2 EIM_BCLK high level width 0.4 ×t×(k+1) — ns
WE3 EIM_BCLK low level width 0.4 ×t×(k+1) — ns
WE4
EIM_ADDRxx
EIM_CSx_B
EIM_WE_B
EIM_OE_B
EIM_BCLK
EIM_EBx_B
EIM_LBA_B
Output Data
...
WE5
WE6 WE7
WE8 WE9
WE10 WE11
WE12 WE13
WE14 WE15
WE16 WE17
WE3
WE2
WE1
Input Data
EIM_WAIT_B
EIM_BCLK
WE19
WE18
WE21
WE20
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WE4 Clock rise to address valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns
WE5 Clock rise to address invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns
WE6 Clock rise to EIM_CSx_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns
WE7 Clock rise to EIM_CSx_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns
WE8 Clock rise to EIM_WE_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns
WE9 Clock rise to EIM_WE_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns
WE10 Clock rise to EIM_OE_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns
WE11 Clock rise to EIM_OE_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns
WE12 Clock rise to EIM_EBx_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns
WE13 Clock rise to EIM_EBx_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns
WE14 Clock rise to EIM_LBA_B valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns
WE15 Clock rise to EIM_LBA_B invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns
WE16 Clock rise to output data valid -0.5 × t × (k+1) - 1.25 -0.5 × t × (k+1) + 2.25 ns
WE17 Clock rise to output data invalid 0.5 × t × (k+1) - 1.25 0.5 × t × (k+1) + 2.25 ns
WE18 Input data setup time to clock rise 2.3 ns
WE19 Input data hold time from clock rise 2 ns
WE20 EIM_WAIT_B setup time to clock rise 2 ns
WE21 EIM_WAIT_B hold time from clock rise 2 ns
1k represents register setting BCD value.
2t is clock period (1/Freq). For 104 MHz, t = 9.165 ns.
Table 41. EIM Bus Timing Parameters (continued)
ID Parameter Min1Max1Unit
Electrical Characteristics
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NXP Semiconductors 57
Figure 14 to Figure 17 provide few examples of basic EIM accesses to external memory devices with the
timing parameters mentioned previously for specific control parameters settings.
Figure 14. Synchronous Memory Read Access, WSC=1
Figure 15. Synchronous Memory, Write Access, WSC=1, WBEA=0 and WADVN=0
Last Valid Address Address v1
D(v1)
EIM_BCLK
EIM_ADDRxx
EIM_DATAxx
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
WE4 WE5
WE6
WE7
WE11
WE13
WE12
WE14
WE15
WE18 WE19
WE6
WE10
Last Valid Address Address V1
D(V1)
EIM_BCLK
EIM_ADDRxx
EIM_DATAxx
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
WE4 WE5
WE6 WE7
WE8 WE9
WE12 WE13
WE14 WE15
WE16 WE17
*F j Lk,, fialmf
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Electrical Characteristics
Figure 16. Muxed Address/Data (A/D) Mode, Synchronous Write Access,
WSC=6,ADVA=0, ADVN=1, and ADH=1
NOTE
In 32-bit muxed address/data (A/D) mode the 16 MSBs are driven on the
data bus.
Figure 17. 16-Bit Muxed A/D Mode, Synchronous Read Access,
WSC=7, RADVN=1, ADH=1, OEA=0
EIM_BCLK
EIM_ADDRxx/
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
Address V1 Write Data
EIM_ADxx
WE4
WE16
WE6
WE7
WE9
WE8
WE10
WE11
WE14 WE15
WE17
WE5
Last Address
Valid
Last
EIM_BCLK
EIM_ADDRxx/
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
Address V1 Data
Address
EIM_ADxx
WE5
WE6
WE7
WE14 WE15
WE10
WE11
WE12 WE13
WE18
WE19
WE4
Valid
end of M\/\J—LM\/\
Electrical Characteristics
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4.9.3.4 General EIM Timing-Asynchronous Mode
Figure 18 through Figure 22 and Table 42 provide timing parameters relative to the chip select (CS) state
for asynchronous and DTACK EIM accesses with corresponding EIM bit fields and the timing
parameters mentioned above.
Asynchronous read and write access length in cycles may vary from what is shown in Figure 18 through
Figure 21 as RWSC, OEN & CSN is configured differently. See the i.MX 6DualPlus/6QuadPlus reference
manual (IMX6DQPRM) for the EIM programming model.
Figure 18. Asynchronous Memory Read Access (RWSC = 5)
Last Valid Address Address V1
D(V1)
EIM_ADDRxx/
EIM_DATA[07:00]
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
Next Address
WE39
WE35
WE37
WE32
WE36
WE38
WE43
WE40
WE31
WE44
INT_CLK
start of
access
end of
access
MAXDI
MAXCSO
MAXCO
EIM_ADxx
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Electrical Characteristics
Figure 19. Asynchronous A/D Muxed Read Access (RWSC = 5)
Figure 20. Asynchronous Memory Write Access
Addr. V1 D(V1)
EIM_ADDRxx/
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
WE39
WE35A
WE37
WE36
WE38
WE40A
WE31
WE44
INT_CLK
start of
access
end of
access
MAXDI
MAXCSO
MAXCO
WE32A
EIM_ADxx
Last Valid Address Address V1
D(V1)
EIM_ADDRxx
EIM_DATAxx
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
Next Address
WE31
WE39
WE33
WE45
WE32
WE40
WE34
WE46
WE42
WE41
Electrical Characteristics
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Figure 21. Asynchronous A/D Muxed Write Access
Figure 22. DTACK Mode Read Access (DAP=0)
EIM_WE_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
WE33
WE45
WE34
WE46
Addr. V1 D(V1)
EIM_ADDRxx/
WE31
WE42
WE41A
WE32A
EIM_DATAxx
EIM_LBA_B
WE39
WE40A
Last Valid Address Address V1
D(V1)
EIM_ADDRxx
EIM_DATAxx[07:00]
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
Next Address
WE39
WE35
WE37
WE32
WE36
WE38
WE43
WE40
WE31
WE44
WE47
WE48
EIM_DTACK_B
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Electrical Characteristics
Figure 23. DTACK Mode Write Access (DAP=0)
Table 42. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2
Ref No. Parameter Determination by Synchronous
measured parameters Min Max Unit
WE31 EIM_CSx_B valid to Address Valid WE4-WE6-CSA×t-3.5-CSA×t3.5-CSA×tns
WE32 Address Invalid to EIM_CSx_B
Invalid
WE7-WE5-CSN×t-3.5-CSN×t3.5-CSN×tns
WE32A
(muxed
A/D)
EIM_CSx_B valid to Address
Invalid
t+WE4-WE7+
(ADVN+ADVA+1-CSA)×t
t-3.5+(ADVN+A
DVA+1-CSA)×t
t+3.5+(ADVN+ADVA+
1-CSA)×t
ns
WE33 EIM_CSx_B Valid to EIM_WE_B
Valid
WE8-WE6+(WEA-WCSA)×t-3.5+(WEA-WCS
A)×t
3.5+(WEA-WCSA)×tns
WE34 EIM_WE_B Invalid to EIM_CSx_B
Invalid
WE7-WE9+(WEN-WCSN)×t -3.5+(WEN-WCS
N)×t
3.5+(WEN-WCSN)×tns
WE35 EIM_CSx_B Valid to EIM_OE_B
Valid
WE10- WE6+(OEA-RCSA)×t -3.5+(OEA-RCS
A)×t
3.5+(OEA-RCSA)×tns
WE35A
(muxed
A/D)
EIM_CSx_B Valid to EIM_OE_B
Valid
WE10-WE6+(OEA+RADVN+R
ADVA+ADH+1-RCSA)×t
-3.5+(OEA+RAD
VN+RADVA+ADH
+1-RCSA)×t
3.5+(OEA+RADVN+RA
DVA+ADH+1-RCSA)×t
ns
WE36 EIM_OE_B Invalid to EIM_CSx_B
Invalid
WE7-WE11+(OEN-RCSN)×t -3.5+(OEN-RCS
N)×t
3.5+(OEN-RCSN)×tns
WE37 EIM_CSx_B Valid to EIM_EBx_B
Valid (Read access)
WE12-WE6+(RBEA-RCSA)×t -3.5+(RBEA- RC
SA)×t
3.5+(RBEA - RCSA)×tns
WE38 EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Read access)
WE7-WE13+(RBEN-RCSN)×t-3.5+
(RBEN-RCSN)×t
3.5+(RBEN-RCSN)×tns
WE39 EIM_CSx_B Valid to EIM_LBA_B
Valid
WE14-WE6+(ADVA-CSA)×t-3.5+
(ADVA-CSA)×t
3.5+(ADVA-CSA)×tns
Last Valid Address Address V1
D(V1)
EIM_ADDRxx
EIM_DATAxx
EIM_WE_B
EIM_LBA_B
EIM_OE_B
EIM_EBx_B
EIM_CSx_B
Next Address
WE31
WE39
WE33
WE45
WE32
WE40
WE34
WE46
WE42
WE41
EIM_DTACK_B
WE47
WE48
Invahd I0 EIM,CSX,B ElMiDTACKiB inpul Io its imernal
Electrical Characteristics
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NXP Semiconductors 63
WE40 EIM_LBA_B Invalid to
EIM_CSx_B Invalid (ADVL is
asserted)
WE7-WE15-CSN×t-3.5-CSN×t3.5-CSN×tns
WE40A
(muxed
A/D)
EIM_CSx_B Valid to EIM_LBA_B
Invalid
WE14-WE6+(ADVN+ADVA+1-
CSA)×t
-3.5+(ADVN+AD
VA+1-CSA)×t
3.5+(ADVN+ADVA
+1-CSA)×t
ns
WE41 EIM_CSx_B Valid to Output Data
Valid
WE16-WE6-WCSA×t-3.5-WCSA×t3.5-WCSA×tns
WE41A
(muxed
A/D)
EIM_CSx_B Valid to Output Data
Valid
WE16-WE6+(WADVN+WADVA
+ADH+1-WCSA)×t
-3.5+(WADVN+
WADVA
+ADH+1-WCSA)
×t
3.5+(WADVN+WADVA
+ADH+1-WCSA)×t
ns
WE42 Output Data Invalid to EIM_CSx_B
Invalid
WE17-WE7-CSN×t-3.5-CSN×t3.5-CSN×tns
MAXCO Output maximum delay from
internal driving
EIM_ADDRxx/control flip-flops to
chip outputs.
10 10 ns
MAXCSO Output maximum delay from
internal chip selects driving
flip-flops to EIM_CSx_B out.
10 10 ns
MAXDI EIM_DATAxx MAXIMUM delay
from chip input data to its internal
flip-flop
5—5ns
WE43 Input Data Valid to EIM_CSx_B
Invalid
MAXCO-MAXCSO+MAXDI MAXCO-MAXCS
O+MAXDI
—ns
WE44 EIM_CSx_B Invalid to Input Data
Invalid
00ns
WE45 EIM_CSx_B Valid to EIM_EBx_B
Valid (Write access)
WE12-WE6+(WBEA-WCSA)×t -3.5+(WBEA-WC
SA)×t
3.5+(WBEA-WCSA)×tns
WE46 EIM_EBx_B Invalid to
EIM_CSx_B Invalid (Write access)
WE7-WE13+(WBEN-WCSN)×t -3.5+(WBEN-WC
SN)×t
3.5+(WBEN-WCSN)×tns
MAXDTI Maximum delay from
EIM_DTACK_B input to its internal
flip-flop + 2 cycles for
synchronization
10 10 ns
WE47 EIM_DTACK_B Active to
EIM_CSx_B Invalid
MAXCO-MAXCSO+MAXDTI MAXCO-MAXCS
O+MAXDTI
—ns
WE48 EIM_CSx_B Invalid to
EIM_DTACK_B invalid
00ns
1For more information on configuration parameters mentioned in this table, see the i.MX 6DualPlus/6QuadPlus reference manual
(IMX6DQPRM).
Table 42. EIM Asynchronous Timing Parameters Relative to Chip Select1, 2 (continued)
Ref No. Parameter Determination by Synchronous
measured parameters Min Max Unit
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Electrical Characteristics
4.10 Multi-Mode DDR Controller (MMDC)
The Multi-mode DDR Controller is a dedicated interface to DDR3/DDR3L/LPDDR2 SDRAM.
4.10.1 MMDC Compatibility with JEDEC-Compliant SDRAMs
The i.MX 6DualPlus/6QuadPlus MMDC supports the following memory types:
LPDDR2 SDRAM compliant to JESD209-2B LPDDR2 JEDEC standard release June, 2009
DDR3/DDR3L SDRAM compliant to JESD79-3D DDR3 JEDEC standard release April, 2008
MMDC operation with the standards stated above is contingent upon the board DDR design adherence to
the DDR design and layout requirements stated in the Hardware Development Guide for i.MX 6Quad,
6Dual, 6DualLite, 6Solo Families of Applications Processors (IMX6DQ6SDLHDG).
4.10.2 MMDC Supported DDR3/DDR3L/LPDDR2 Configurations
The table below shows the supported DDR3/DDR3L/LPDDR2 configurations:
4.11 General-Purpose Media Interface (GPMI) Timing
The i.MX 6DualPlus/6QuadPlus GPMI controller is a flexible interface NAND Flash controller with 8-bit
data width, up to 200 MB/s I/O speed and individual chip select. It supports Asynchronous timing mode,
Source Synchronous timing mode, and Samsung Toggle timing mode separately described in the following
subsections.
2In this table:
t means clock period from axi_clk frequency.
CSA means register setting for WCSA when in write operations or RCSA when in read operations.
CSN means register setting for WCSN when in write operations or RCSN when in read operations.
ADVN means register setting for WADVN when in write operations or RADVN when in read operations.
ADVA means register setting for WADVA when in write operations or RADVA when in read operations.
Table 43. i.MX 6DualPlus/6QuadPlus Supported DDR3/DDR3L/LPDDR2 Configurations
Parameter LPDDR2 DDR3 DDR3L
Clock frequency 400 MHz 532 MHz 532 MHz
Bus width 32-bit per channel 16/32/64-bit 16/32/64-bit
Channel Dual Single Single
Chip selects 2 per channel 2 2
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NXP Semiconductors 65
4.11.1 Asynchronous Mode AC Timing (ONFI 1.0 Compatible)
Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The
Maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 24 through Figure 27
depict the relative timing between GPMI signals at the module level for different operations under
Asynchronous mode. Table 44 describes the timing parameters (NF1–NF17) that are shown in the figures.
Figure 24. Command Latch Cycle Timing Diagram
Figure 25. Address Latch Cycle Timing Diagram
Figure 26. Write Data Latch Cycle Timing Diagram
Command
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NF6
NF5
NF1
NF3
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Figure 27. Read Data Latch Cycle Timing Diagram (Non-EDO Mode)
Figure 28. Read Data Latch Cycle Timing Diagram (EDO Mode)
Table 44. Asynchronous Mode Timing Parameters1
ID Parameter Symbol
Timing
T = GPMI Clock Cycle Unit
Min Max
NF1 NAND_CLE setup time tCLS (AS + DS) ×T - 0.12 [see 2,3]ns
NF2 NAND_CLE hold time tCLH DH ×T - 0.72 [see 2]ns
NF3 NAND_CEx_B setup time tCS (AS + DS + 1) ×T [see 3,2]ns
NF4 NAND_CEx_B hold time tCH (DH+1) ×T - 1 [see 2]ns
NF5 NAND_WE_B pulse width tWP DS ×T [see 2]ns
NF6 NAND_ALE setup time tALS (AS + DS) ×T - 0.49 [see 3,2]ns
NF7 NAND_ALE hold time tALH (DH ×T - 0.42 [see 2]ns
NF8 Data setup time tDS DS ×T - 0.26 [see 2]ns
NF9 Data hold time tDH DH ×T - 1.37 [see 2]ns
NF10 Write cycle time tWC (DS + DH) ×T [see 2]ns
NF11 NAND_WE_B hold time tWH DH ×T [see 2]ns
NF12 Ready to NAND_RE_B low tRR4(AS + 2) ×T [see 3,2]—ns
NF13 NAND_RE_B pulse width tRP DS ×T [see 2]ns
NF14 READ cycle time tRC (DS + DH) ×T [see 2]ns
NF15 NAND_RE_B high hold time tREH DH ×T [see 2]ns
Data from NF
NF14
NF15
NF17
NF16
NF12
NF13
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NF15
NF17
NF16
NF12
NF13
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Electrical Characteristics
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NXP Semiconductors 67
In EDO mode (Figure 28), NF16/NF17 are different from the definition in non-EDO mode (Figure 27).
They are called tREA/tRHOH (NAND_RE_B access time/NAND_RE_B HIGH to output hold). The
typical value for them are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO
mode, GPMI will sample NAND_DATAxx at rising edge of delayed NAND_RE_B provided by an
internal DPLL. The delay value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter
of the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM)). The typical value of this control
register is 0x8 at 50 MT/s EDO mode. However, if the board delay is large enough and cannot be ignored,
the delay value should be made larger to compensate the board delay.
NF16 Data setup on read tDSR (DS ×T -0.67)/18.38 [see 5,6]ns
NF17 Data hold on read tDHR 0.82/11.83 [see 5,6]—ns
1The GPMI asynchronous mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2 AS minimum value can be 0, while DS/DH minimum value is 1.
3T = GPMI clock period -0.075ns (half of maximum p-p jitter).
4NF12 is met automatically by the design.
5Non-EDO mode.
6EDO mode, GPMI clock 100 MHz
(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).
Table 44. Asynchronous Mode Timing Parameters1 (continued)
ID Parameter Symbol
Timing
T = GPMI Clock Cycle Unit
Min Max
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Electrical Characteristics
4.11.2 Source Synchronous Mode AC Timing (ONFI 2.x Compatible)
Figure 29 shows the write and read timing of Source Synchronous mode.
Figure 29. Source Synchronous Mode Command and Address Timing Diagram
NF18
NF25 NF26
NF25 NF26
NF20
NF21
NF20
NF23
NF24
NF19
NF22
NF21
CMD ADD
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NAND_ALE
NAND_WE/RE_B
NAND_CLK
NAND_DQS
NAND_DQS
Output enable
NAND_DATA[7:0]
NAND_DATA[7:0]
Output enable
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NXP Semiconductors 69
Figure 30. Source Synchronous Mode Data Write Timing Diagram
Figure 31. Source Synchronous Mode Data Read Timing Diagram
NF23
NF18
NF25
NF26
NF27
NF25
NF26
NF28 NF28
NF29 NF29
NF23 NF24
NF24
NF19
NF27
NF22
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NF18
NF25
NF26
NF25
NF26
NF23 NF24
NF24
NF19
NF22
NF25
NF26
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Figure 32. NAND_DQS/NAND_DQ Read Valid Window
Figure 32 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For Source
Synchronous mode, the typical value of tDQSQ is 0.85 ns (max) and 1 ns (max) for tQHS at 200MB/s.
GPMI will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal,
which can be provided by an internal DPLL. The delay value can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX
6DualPlus/6QuadPlus reference manual (IMX6DQPRM)). Generally, the typical delay value of this
register is equal to 0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large
enough and cannot be ignored, the delay value should be made larger to compensate the board delay.
Table 45. Source Synchronous Mode Timing Parameters1
1The GPMI source synchronous mode output timing can be controlled by the module’s internal registers
GPMI_TIMING2_CE_DELAY, GPMI_TIMING_PREAMBLE_DELAY, GPMI_TIMING2_POST_DELAY. This AC timing depends
on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.
ID Parameter Symbol
Timing
T = GPMI Clock Cycle Unit
Min Max
NF18 NAND_CEx_B access time tCE CE_DELAY ×T - 0.79 [see 2]
2T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).
ns
NF19 NAND_CEx_B hold time tCH 0.5 ×tCK - 0.63 [see 2]ns
NF20 Command/address NAND_DATAxx setup time tCAS 0.5 ×tCK - 0.05 ns
NF21 Command/address NAND_DATAxx hold time tCAH 0.5 ×tCK - 1.23 ns
NF22 clock period tCK ns
NF23 preamble delay tPRE PRE_DELAY ×T - 0.29 [see 2]ns
NF24 postamble delay tPOST POST_DELAY ×T - 0.78 [see 2]ns
NF25 NAND_CLE and NAND_ALE setup time tCALS 0.5 ×tCK - 0.86 ns
NF26 NAND_CLE and NAND_ALE hold time tCALH 0.5 ×tCK - 0.37 ns
NF27 NAND_CLK to first NAND_DQS latching transition tDQSS T - 0.41 [see 2]ns
NF28 Data write setup tDS 0.25 ×tCK - 0.35
NF29 Data write hold tDH 0.25 ×tCK - 0.85
NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ 2.06
NF31 NAND_DQS/NAND_DQ read hold skew tQHS 1.95
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NXP Semiconductors 71
4.11.3 Samsung Toggle Mode AC Timing
4.11.3.1 Command and Address Timing
Samsung Toggle mode command and address timing is the same as ONFI 1.0 compatible Async mode AC
timing. See Section 4.11.1, “Asynchronous Mode AC Timing (ONFI 1.0 Compatible)” for details.
4.11.3.2 Read and Write Timing
Figure 33. Samsung Toggle Mode Data Write Timing
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Electrical Characteristics
Figure 34. Samsung Toggle Mode Data Read Timing
Table 46. Samsung Toggle Mode Timing Parameters1
ID Parameter Symbol
Timing
T = GPMI Clock Cycle Unit
Min Max
NF1 NAND_CLE setup time tCLS (AS + DS) ×T - 0.12 [see 2,3]—
NF2 NAND_CLE hold time tCLH DH ×T - 0.72 [see 2]—
NF3 NAND_CEx_B setup time tCS (AS + DS) ×T - 0.58 [see 3,2]—
NF4 NAND_CEx_B hold time tCH DH ×T - 1 [see 2]—
NF5 NAND_WE_B pulse width tWP DS ×T [see 2]—
NF6 NAND_ALE setup time tALS (AS + DS) ×T - 0.49 [see 3,2]—
NF7 NAND_ALE hold time tALH DH ×T - 0.42 [see 2]—
NF8 Command/address NAND_DATAxx setup time tCAS DS ×T - 0.26 [see 2]—
NF9 Command/address NAND_DATAxx hold time tCAH DH ×T - 1.37 [see 2]—
NF18 NAND_CEx_B access time tCE CE_DELAY ×T [see 4, 2]—ns
NF22 clock period tCK ns
NF23 preamble delay tPRE PRE_DELAY ×T [see 5,2]—ns
NF24 postamble delay tPOST POST_DELAY ×T +0.43 [see 2]— ns
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NXP Semiconductors 73
Figure 32 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid window. For DDR
Toggle mode, the typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI
will sample NAND_DATA[7:0] at both rising and falling edge of a delayed NAND_DQS signal, which is
provided by an internal DPLL. The delay value of this register can be controlled by GPMI register
GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX
6DualPlus/6QuadPlus reference manual (IMX6DQPRM)). Generally, the typical delay value is equal to
0x7 which means 1/4 clock cycle delay expected. However, if the board delay is large enough and cannot
be ignored, the delay value should be made larger to compensate the board delay.
4.12 External Peripheral Interface Parameters
The following subsections provide information on external peripheral interfaces.
4.12.1 AUDMUX Timing Parameters
The AUDMUX provides a programmable interconnect logic for voice, audio, and data routing between
internal serial interfaces (SSIs) and external serial interfaces (audio and voice codecs). The AC timing of
AUDMUX external pins is governed by the SSI module. For more information, see the respective SSI
electrical specifications found within this document.
4.12.2 ECSPI Timing Parameters
This section describes the timing parameters of the ECSPI block. The ECSPI has separate timing
parameters for master and slave modes.
NF28 Data write setup tDS60.25 ×tCK - 0.32 ns
NF29 Data write hold tDH60.25 ×tCK - 0.79 ns
NF30 NAND_DQS/NAND_DQ read setup skew tDQSQ7—3.18
NF31 NAND_DQS/NAND_DQ read hold skew tQHS7—3.27
1The GPMI toggle mode output timing can be controlled by the module’s internal registers
HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.
This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.
2 AS minimum value can be 0, while DS/DH minimum value is 1.
3T = tCK (GPMI clock period) -0.075ns (half of maximum p-p jitter).
4CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is met automatically by the design. Read/Write operation is
started with enough time of ALE/CLE assertion to low level.
5PRE_DELAY+1) (AS+DS).
6Shown in Figure 30.
7Shown in Figure 31.
Table 46. Samsung Toggle Mode Timing Parameters1 (continued)
ID Parameter Symbol
Timing
T = GPMI Clock Cycle Unit
Min Max
Io ECSPILSSX Time‘
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4.12.2.1 ECSPI Master Mode Timing
Figure 35 depicts the timing of ECSPI in master mode and Table 47 lists the ECSPI master mode timing
characteristics.
Figure 35. ECSPI Master Mode Timing Diagram
Table 47. ECSPI Master Mode Timing Parameters
ID Parameter Symbol Min Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
Slow group1
Fast group2
ECSPIx_SCLK Cycle Time–Write
1ECSPI slow includes:
ECSPI1/DISP0_DAT22, ECSPI1/KEY_COL1, ECSPI1/CSI0_DAT6,
ECSPI2/EIM_OE, ECSPI2/ ECSPI2/CSI0_DAT10, ECSPI3/DISP0_DAT2
2ECSPI fast includes:
ECSPI1/EIM_D17, ECSPI4/EIM_D22, ECSPI5/SD2_DAT0, ECSPI5/SD1_DAT0
tclk
55
40
15
—ns
CS2 ECSPIx_SCLK High or Low Time–Read
Slow group1
Fast group2
ECSPIx_SCLK High or Low Time–Write
tSW
26
20
7
—ns
CS3 ECSPIx_SCLK Rise or Fall3
3See specific I/O AC parameters Section 4.7, “I/O AC Parameters.”
tRISE/FALL ——ns
CS4 ECSPIx_SSx pulse width tCSLH Half ECSPIx_SCLK period ns
CS5 ECSPIx_SSx Lead Time (CS setup time) tSCS Half ECSPIx_SCLK period - 4 ns
CS6 ECSPIx_SSx Lag Time (CS hold time) tHCS Half ECSPIx_SCLK period - 2 ns
CS7 ECSPIx_MOSI Propagation Delay (CLOAD =20pF) t
PDmosi -1 1 ns
CS8 ECSPIx_MISO Setup Time
Slow group1
Fast group2
tSmiso
21.5
16
—ns
CS9 ECSPIx_MISO Hold Time tHmiso 0—ns
CS10 ECSPIx_RDY to ECSPIx_SSx Time4
4ECSPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.
tSDRY 5—ns
CS1
CS7
CS2
CS2
CS4
CS6 CS5
CS8 CS9
ECSPIx_SCLK
ECSPIx_SS_B
ECSPIx_MOSI
ECSPIx_MISO
ECSPIx_RDY_B
CS10
CS3
CS3
Note: ECSPIx_MOSI is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be
connected between a single master and a single slave.
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4.12.2.2 ECSPI Slave Mode Timing
Figure 36 depicts the timing of ECSPI in slave mode and Table 48 lists the ECSPI slave mode timing
characteristics.
Figure 36. ECSPI Slave Mode Timing Diagram
Table 48. ECSPI Slave Mode Timing Parameters
ID Parameter Symbol Min Max Unit
CS1 ECSPIx_SCLK Cycle Time–Read
Slow group1
Fast group2
ECSPIx_SCLK Cycle Time–Write
1ECSPI slow includes:
ECSPI1/DISP0_DAT22, ECSPI1/KEY_COL1, ECSPI1/CSI0_DAT6,
ECSPI2/EIM_OE, ECSPI2/DISP0_DAT17, ECSPI2/CSI0_DAT10, ECSPI3/DISP0_DAT2
2ECSPI fast includes:
ECSPI1/EIM_D17, ECSPI4/EIM_D22, ECSPI5/SD2_DAT0, ECSPI5/SD1_DAT0
tclk
55
40
15
—ns
CS2 ECSPIx_SCLK High or Low Time–Read
Slow group1
Fast group2
ECSPIx_SCLK High or Low Time–Write
tSW
26
20
7
—ns
CS4 ECSPIx_SSx pulse width tCSLH Half ECSPIx_SCLK period ns
CS5 ECSPIx_SSx Lead Time (CS setup time) tSCS 5—ns
CS6 ECSPIx_SSx Lag Time (CS hold time) tHCS 5—ns
CS7 ECSPIx_MOSI Setup Time tSmosi 4—ns
CS8 ECSPIx_MOSI Hold Time tHmosi 4—ns
CS9 ECSPIx_MISO Propagation Delay (CLOAD =20pF)
Slow group1
Fast group2
tPDmiso 4
25
17
ns
CS1
CS7 CS8
CS2
CS2
CS4
CS6 CS5
CS9
ECSPIx_SCLK
ECSPIx_SS_B
ECSPIx_MISO
ECSPIx_MOSI
Note: ECSPIx_MISO is always driven (not tri-stated) between actual data transmissions. This limits the ECSPI to be con-
nected between a single master and a single slave.
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4.12.3 Enhanced Serial Audio Interface (ESAI) Timing Parameters
The ESAI consists of independent transmitter and receiver sections, each section with its own clock
generator. Table 49 shows the interface timing values. The number field in the table refers to timing
signals found in Figure 37 and Figure 38.
Table 49. Enhanced Serial Audio Interface (ESAI) Timing
ID Parameter1,2 Symbol Expression2Min Max Condition3Unit
62 Clock cycle4tSSICC 4 × Tc
4 × Tc
30.0
30.0
i ck
i ck
ns
63 Clock high period:
For internal clock
For external clock
2 × Tc 9.0
2 × Tc
6
15
ns
64 Clock low period:
For internal clock
For external clock
2 × Tc 9.0
2 × Tc
6
15
ns
65 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) high
19.0
7.0
x ck
i ck a
ns
66 ESAI_RX_CLK rising edge to ESAI_RX_FS out (bl) low
19.0
7.0
x ck
i ck a
ns
67 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr)
high5
19.0
9.0
x ck
i ck a
ns
68 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wr) low5
19.0
9.0
x ck
i ck a
ns
69 ESAI_RX_CLK rising edge to ESAI_RX_FS out (wl) high
19.0
6.0
x ck
i ck a
ns
70 ESAI_RX_CLK rising edge to ESAI_RX_FSout (wl) low
17.0
7.0
x ck
i ck a
ns
71 Data in setup time before ESAI_RX_CLK (serial clock in
synchronous mode) falling edge
12.0
19.0
x ck
i ck
ns
72 Data in hold time after ESAI_RX_CLK falling edge
3.5
9.0
x ck
i ck
ns
73 ESAI_RX_FS input (bl, wr) high before ESAI_RX_CLK
falling edge5
2.0
19.0
x ck
i ck a
ns
74 ESAI_RX_FS input (wl) high before ESAI_RX_CLK
falling edge
2.0
19.0
x ck
i ck a
ns
75 ESAI_RX_FS input hold time after ESAI_RX_CLK falling
edge
2.5
8.5
x ck
i ck a
ns
78 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) high
19.0
8.0
x ck
i ck
ns
79 ESAI_TX_CLK rising edge to ESAI_TX_FS out (bl) low
20.0
10.0
x ck
i ck
ns
80 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr)
high5
20.0
10.0
x ck
i ck
ns
Electrical Characteristics
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81 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wr) low5
22.0
12.0
x ck
i ck
ns
82 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) high
19.0
9.0
x ck
i ck
ns
83 ESAI_TX_CLK rising edge to ESAI_TX_FS out (wl) low
20.0
10.0
x ck
i ck
ns
84 ESAI_TX_CLK rising edge to data out enable from high
impedance
22.0
17.0
x ck
i ck
ns
86 ESAI_TX_CLK rising edge to data out valid
19.0
13.0
x ck
i ck
ns
87 ESAI_TX_CLK rising edge to data out high impedance 67
21.0
16.0
x ck
i ck
ns
89 ESAI_TX_FS input (bl, wr) setup time before
ESAI_TX_CLK falling edge5
2.0
18.0
x ck
i ck
ns
90 ESAI_TX_FS input (wl) setup time before ESAI_TX_CLK
falling edge
2.0
18.0
x ck
i ck
ns
91 ESAI_TX_FS input hold time after ESAI_TX_CLK falling
edge
4.0
5.0
x ck
i ck
ns
95 ESAI_RX_HF_CLK/ESAI_TX_HF_CLK clock cycle 2 x TC15 — ns
96 ESAI_TX_HF_CLK input rising edge to ESAI_TX_CLK
output
——18.0ns
97 ESAI_RX_HF_CLK input rising edge to ESAI_RX_CLK
output
——18.0ns
1i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that ESAI_TX_CLK and ESAI_RX_CLK are the same clock)
2bl = bit length
wl = word length
wr = word length relative
3ESAI_TX_CLK(ESAI_TX_CLK pin) = transmit clock
ESAI_RX_CLK(ESAI_RX_CLK pin) = receive clock
ESAI_TX_FS(ESAI_TX_FS pin) = transmit frame sync
ESAI_RX_FS(ESAI_RX_FS pin) = receive frame sync
ESAI_TX_HF_CLK(ESAI_TX_HF_CLK pin) = transmit high frequency clock
ESAI_RX_HF_CLK(ESAI_RX_HF_CLK pin) = receive high frequency clock
4For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
5The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync
signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the
second-to-last bit clock of the first word in the frame.
6Periodically sampled and not 100% tested.
Table 49. Enhanced Serial Audio Interface (ESAI) Timing (continued)
ID Parameter1,2 Symbol Expression2Min Max Condition3Unit
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Electrical Characteristics
Figure 37. ESAI Transmitter Timing
ESAI_TX_CLK
(Input/Output)
ESAI_TX_FS
(Bit)
Out
ESAI_TX_FS
(Word)
Out
Data Out
ESAI_TX_FS
(Bit) In
ESAI_TX_FS
(Word) In
62
64
78 79
82 83
87
8686
84
91
89
90 91
63
Last BitFirst Bit
Electrical Characteristics
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Figure 38. ESAI Receiver Timing
ESAI_RX_CLK
(Input/Output)
ESAI_RX_FS
(Bit) Out
ESAI_RX_FS
(Word) Out
Data In
ESAI_RX_FS
(Bit) In
ESAI_RX_FS
(Word) In
62
64
65
69 70
72
71
75
73
74 75
63
66
First Bit Last Bit
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Electrical Characteristics
4.12.4 Ultra High Speed SD/SDIO/MMC Host Interface (uSDHC)
AC Timing
This section describes the electrical information of the uSDHC, which includes SD/eMMC4.3 (Single
Data Rate) timing and eMMC4.4/4.1 (Dual Date Rate) timing.
4.12.4.1 SD/eMMC4.3 (Single Data Rate) AC Timing
Figure 39 depicts the timing of SD/eMMC4.3, and Table 50 lists the SD/eMMC4.3 timing characteristics.
Figure 39. SD/eMMC4.3 Timing
Table 50. SD/eMMC4.3 Interface Timing Specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency (Low Speed) fPP10400kHz
Clock Frequency (SD/SDIO Full Speed/High Speed) fPP20 25/50 MHz
Clock Frequency (MMC Full Speed/High Speed) fPP30 20/52 MHz
Clock Frequency (Identification Mode) fOD 100 400 kHz
SD2 Clock Low Time tWL 7—ns
SD3 Clock High Time tWH 7—ns
SD4 Clock Rise Time tTLH —3ns
SD5 Clock Fall Time tTHL —3ns
eSDHC Output/Card Inputs SD_CMD, SD_DATAx (Reference to SDx_CLK)
SD6 eSDHC Output Delay tOD –6.6 3.6 ns
SD1
SD3
SD5
SD4
SD7
SDx_CLK
SD2
SD8
SD6
Output from uSDHC to card
Input from card to uSDHC
SDx_DATA[7:0]
SDx_DATA[7:0]
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4.12.4.2 eMMC4.4/4.41 (Dual Data Rate) eSDHCv3 AC Timing
Figure 40 depicts the timing of eMMC4.4/4.41. Table 51 lists the eMMC4.4/4.41 timing characteristics.
Be aware that only SDx_DATAx is sampled on both edges of the clock (not applicable to SD_CMD).
Figure 40. eMMC4.4/4.41 Timing
eSDHC Input/Card Outputs SD_CMD, SD_DATAx (Reference to SDx_CLK)
SD7 eSDHC Input Setup Time tISU 2.5 — ns
SD8 eSDHC Input Hold Time4tIH 1.5 — ns
1In low speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.
2In normal (full) speed mode for SD/SDIO card, clock frequency can be any value between 025 MHz. In high-speed mode,
clock frequency can be any value between 050 MHz.
3In normal (full) speed mode for MMC card, clock frequency can be any value between 020 MHz. In high-speed mode, clock
frequency can be any value between 052 MHz.
4To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.
Table 51. eMMC4.4/4.41 Interface Timing Specification
ID Parameter Symbols Min Max Unit
Card Input Clock1
1Clock duty cycle will be in the range of 47% to 53%.
SD1 Clock Frequency (EMMC4.4 DDR) fPP 052MHz
SD1 Clock Frequency (SD3.0 DDR) fPP 050MHz
uSDHC Output / Card Inputs SD_CMD, SD_DATAx (Reference to SD_CLK)
SD2 uSDHC Output Delay tOD 2.8 6.8 ns
uSDHC Input / Card Outputs SD_CMD, SD_DATAx (Reference to SD_CLK)
SD3 uSDHC Input Setup Time tISU 1.7 — ns
SD4 uSDHC Input Hold Time tIH 1.5 — ns
Table 50. SD/eMMC4.3 Interface Timing Specification (continued)
ID Parameter Symbols Min Max Unit
SD1
SD3
Output from eSDHCv3 to card
Input from card to eSDHCv3
SDx_DATA[7:0]
SDx_CLK
SD4
SD2
......
......
SDx_DATA[7:0]
SD2
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Electrical Characteristics
4.12.4.3 SDR50/SDR104 AC Timing
Figure 41 depicts the timing of SDR50/SDR104, and Table 52 lists the SDR50/SDR104 timing
characteristics.
Figure 41. SDR50/SDR104 Timing
Table 52. SDR50/SDR104 Interface Timing Specification
ID Parameter Symbols Min Max Unit
Card Input Clock
SD1 Clock Frequency Period tCLK 4.8 — ns
SD2 Clock Low Time tCL 0.46 ×tCLK 0.54 ×tCLK ns
SD3 Clock High Time tCH 0.46 ×tCLK 0.54 ×tCLK ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)
SD4 uSDHC Output Delay tOD –3 1 ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)
SD5 uSDHC Output Delay tOD –1.6 0.74 ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to SDx_CLK)
SD6 uSDHC Input Setup Time tISU 2.5 — ns
SD7 uSDHC Input Hold Time tIH 1.5 — ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to SDx_CLK)1
1Data window in SDR100 mode is variable.
SD8 Card Output Data Window tODW 0.5 ×tCLK —ns
Output from uSDHC to card
Input from card to uSDHC
SCK
SD4
SD3
SD5
S
D
3
SD8
SD7
SD6
SD1
SD2
F6134
Electrical Characteristics
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4.12.4.4 Bus Operation Condition for 3.3 V and 1.8 V Signaling
Signaling level of SD/eMMC4.3 and eMMC4.4/4.41 modes is 3.3 V. Signaling level of SDR104/SDR50
mode is 1.8 V. The DC parameters for the NVCC_SD1, NVCC_SD2, and NVCC_SD3 supplies are
identical to those shown in Table 22, “GPIO I/O DC Parameters,” on page 40.
4.12.5 Ethernet Controller (ENET) AC Electrical Specifications
4.12.5.1 ENET MII Mode Timing
This subsection describes MII receive, transmit, asynchronous inputs, and serial management signal
timings.
4.12.5.1.1 MII Receive Signal Timing (ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER, and ENET_RX_CLK)
The receiver functions correctly up to an ENET_RX_CLK maximum frequency of 25 MHz + 1%. There
is no minimum frequency requirement. Additionally, the processor clock frequency must exceed twice the
ENET_RX_CLK frequency.
Figure 42 shows MII receive signal timings. Table 53 describes the timing parameters (M1–M4) shown in
the figure.
Figure 42. MII Receive Signal Timing Diagram
1 ENET_RX_EN, ENET_RX_CLK, and ENET0_RXD0 have the same timing in 10 Mbps 7-wire interface mode.
Table 53. MII Receive Signal Timing
ID Characteristic1Min Max Unit
M1 ENET_RX_DATA3,2,1,0, ENET_RX_EN, ENET_RX_ER to
ENET_RX_CLK setup
5— ns
M2 ENET_RX_CLK to ENET_RX_DATA3,2,1,0, ENET_RX_EN,
ENET_RX_ER hold
5— ns
M3 ENET_RX_CLK pulse width high 35% 65% ENET_RX_CLK period
M4 ENET_RX_CLK pulse width low 35% 65% ENET_RX_CLK period
ENET_RX_CLK (input)
ENET_RX_DATA3,2,1,0
M3
M4
M1 M2
ENET_RX_ER
ENET_RX_EN
(inputs)
—/ DATA3,2,1,0 Oi ‘0 manomfl
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Electrical Characteristics
4.12.5.1.2 MII Transmit Signal Timing
(ENET_TX_DATA3,2,1,0, ENET_TX_EN, ENET_TX_ER, and ENET_TX_CLK)
The transmitter functions correctly up to an ENET_TX_CLK maximum frequency of 25 MHz + 1%.
There is no minimum frequency requirement. Additionally, the processor clock frequency must exceed
twice the ENET_TX_CLK frequency.
Figure 43 shows MII transmit signal timings. Table 54 describes the timing parameters (M5–M8) shown
in the figure.
Figure 43. MII Transmit Signal Timing Diagram
1 ENET_TX_EN, ENET_TX_CLK, and ENET0_TXD0 have the same timing in 10-Mbps 7-wire interface mode.
4.12.5.1.3 MII Asynchronous Inputs Signal Timing (ENET_CRS and ENET_COL)
Figure 44 shows MII asynchronous input timings. Table 55 describes the timing parameter (M9) shown in
the figure.
Figure 44. MII Async Inputs Timing Diagram
Table 54. MII Transmit Signal Timing
ID Characteristic1Min Max Unit
M5 ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER invalid
5— ns
M6 ENET_TX_CLK to ENET_TX_DATA3,2,1,0, ENET_TX_EN,
ENET_TX_ER valid
—20 ns
M7 ENET_TX_CLK pulse width high 35% 65% ENET_TX_CLK period
M8 ENET_TX_CLK pulse width low 35% 65% ENET_TX_CLK period
ENET_TX_CLK (input)
ENET_TX_DATA3,2,1,0
M7
M8
M5
M6
ENET_TX_ER
ENET_TX_EN
(outputs)
ENET_CRS, ENET_COL
M9
Electrical Characteristics
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1 ENET_COL has the same timing in 10-Mbit 7-wire interface mode.
4.12.5.1.4 MII Serial Management Channel Timing (ENET_MDIO and ENET_MDC)
The MDC frequency is designed to be equal to or less than 2.5 MHz to be compatible with the IEEE 802.3
MII specification. However the ENET can function correctly with a maximum MDC frequency of
15 MHz.
Figure 45 shows MII asynchronous input timings. Table 56 describes the timing parameters (M10–M15)
shown in the figure.
Figure 45. MII Serial Management Channel Timing Diagram
Table 55. MII Asynchronous Inputs Signal Timing
ID Characteristic Min Max Unit
M91ENET_CRS to ENET_COL minimum pulse width 1.5 ENET_TX_CLK period
Table 56. MII Serial Management Channel Timing
ID Characteristic Min Max Unit
M10 ENET_MDC falling edge to ENET_MDIO output invalid
(minimum propagation delay)
0— ns
M11 ENET_MDC falling edge to ENET_MDIO output valid
(maximum propagation delay)
—5 ns
M12 ENET_MDIO (input) to ENET_MDC rising edge setup 18 ns
M13 ENET_MDIO (input) to ENET_MDC rising edge hold 0 ns
M14 ENET_MDC pulse width high 40% 60% ENET_MDC period
M15 ENET_MDC pulse width low 40% 60% ENET_MDC period
ENET_MDC (output)
ENET_MDIO (output)
M14
M15
M10
M11
M12 M13
ENET_MDIO (input)
mfifl #0
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Electrical Characteristics
4.12.5.2 RMII Mode Timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET0_TXD[1:0], ENET_RXD[1:0] and ENET_RX_ER.
Figure 46 shows RMII mode timings. Table 57 describes the timing parameters (M16–M21) shown in the
figure.
Figure 46. RMII Mode Signal Timing Diagram
Table 57. RMII Signal Timing
ID Characteristic Min Max Unit
M16 ENET_CLK pulse width high 35% 65% ENET_CLK period
M17 ENET_CLK pulse width low 35% 65% ENET_CLK period
M18 ENET_CLK to ENET0_TXD[1:0], ENET_TX_EN invalid 4 ns
M19 ENET_CLK to ENET0_TXD[1:0], ENET_TX_EN valid 13.5 ns
M20 ENET_RXD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to
ENET_CLK setup
4— ns
M21 ENET_CLK to ENET_RXD[1:0], ENET_RX_EN, ENET_RX_ER hold 2 ns
ENET_CLK (input)
ENET_TX_EN
M16
M17
M18
M19
M20 M21
ENET_RXD[1:0]
ENET0_TXD[1:0] (output)
ENET_RX_ER
ENET_RX_EN (input)
RGM | I_TXC (at transm'rlmr) RGMILTXDn (n = 0 to 3} RGM|I_TX_CTL RGM|I_TXC (a‘ receiver) XXXX . . . I X TXEN X TXERR X: X _. ‘leewR )L
Electrical Characteristics
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4.12.5.3 RGMII Signal Switching Specifications
The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver
devices.
Figure 47. RGMII Transmit Signal Timing Diagram Original
Table 58. RGMII Signal Switching Specifications1
1The timings assume the following configuration:
DDR_SEL = (11)b
DSE (drive-strength) = (111)b
Symbol Description Min Max Unit
Tcyc2
2For 10 Mbps and 100 Mbps, Tcyc will scale to 400 ns ±40 ns and 40 ns ±4 ns respectively.
Clock cycle duration 7.2 8.8 ns
TskewT3
3For all versions of RGMII prior to 2.0; This implies that PC board design will require clocks to be routed such that an additional
delay of greater than 1.2 ns and less than 1.7 ns will be added to the associated clock signal. For 10/100, the max value is
unspecified.
Data to clock output skew at transmitter -100 900 ps
TskewR3Data to clock input skew at receiver 1 2.6 ns
Duty_G4
4Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long
as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned
between.
Duty cycle for Gigabit 45 55 %
Duty_T4Duty cycle for 10/100T 40 60 %
Tr/Tf Rise/fall time (20–80%) 0.75 ns
RGMII_RXC (at transmitter) RGMII_RXDn (n = o to 3) X X RGMII_RX_CTL Rm" . RGMII_RXC (at rece'rver) m RGMII_RXC (source of data)lmemal delay RGMII_RXDn (n = 0 lo 3) X X RGMII_RX_CTL " ERR TsetupR H—Ffi—h’madk . RGMII_RXC (at receiver) m
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Electrical Characteristics
Figure 48. RGMII Receive Signal Timing Diagram Original
Figure 49. RGMII Receive Signal Timing Diagram with Internal Delay
4.12.6 Flexible Controller Area Network (FlexCAN) AC Electrical
Specifications
The Flexible Controller Area Network (FlexCAN) module is a communication controller implementing
the CAN protocol according to the CAN 2.0B protocol specification.The processor has two CAN modules
available for systems design. Tx and Rx ports for both modules are multiplexed with other I/O pins. See
the IOMUXC chapter of the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM) to see which
pins expose Tx and Rx pins; these ports are named FLEXCAN_TX and FLEXCAN_RX, respectively.
4.12.7 HDMI Module Timing Parameters
4.12.7.1 Latencies and Timing Information
Power-up time (time between TX_PWRON assertion and TX_READY assertion) for the HDMI 3D Tx
PHY while operating with the slowest input reference clock supported (13.5 MHz) is 3.35 ms.
TPI VS‘MG 0 V Vwms x wusmum ; muscmp 1: g l 2" gm, TMDSDATANI’] a museum
Electrical Characteristics
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NXP Semiconductors 89
Power-up time for the HDMI 3D Tx PHY while operating with the fastest input reference clock supported
(340 MHz) is 133 μs.
4.12.7.2 Electrical Characteristics
The table below provides electrical characteristics for the HDMI 3D Tx PHY. The following three figures
illustrate various definitions and measurement conditions specified in the table below.
Figure 50. Driver Measuring Conditions
Figure 51. Driver Definitions
Figure 52. Source Termination
Table 59. Electrical Characteristics
Symbol Parameter Condition Min Typ Max Unit
Operating conditions for HDMI
avddtmds Termination supply voltage 3.15 3.3 3.45 V
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4.12.8 Switching Characteristics
Table 60 describes switching characteristics for the HDMI 3D Tx PHY. Figure 53 to Figure 57 illustrate
various parameters specified in table.
NOTE
All dynamic parameters related to the TMDS line drivers’ performance
imply the use of assembly guidelines.
RTTermination resistance 45 50 55 Ω
TMDS drivers DC specifications
VOFF Single-ended standby voltage RT = 50 Ω
For measurement conditions and
definitions, see the first two figures
above.
Compliance point TP1 as defined in
the HDMI specification, version 1.3a,
section 4.2.4.
avddtmds ± 10 mV mV
VSWING Single-ended output swing voltage 400 600 mV
VHSingle-ended output high voltage
For definition, see the second
figure above.
If attached sink supports TMDSCLK <
or = 165 MHz
avddtmds ± 10 mV mV
If attached sink supports TMDSCLK >
165 MHz
avddtmds
– 200 mV
— avddtmds
+ 10 mV
mV
VLSingle-ended output low voltage
For definition, see the second
figure above.
If attached sink supports TMDSCLK <
or = 165 MHz
avddtmds
– 600 mV
— avddtmds
– 400mV
mV
If attached sink supports TMDSCLK >
165 MHz
avddtmds
– 700 mV
— avddtmds
– 400 mV
mV
RTERM Differential source termination load
(inside HDMI 3D Tx PHY)
Although the HDMI 3D Tx PHY
includes differential source
termination, the user-defined value
is set for each single line (for
illustration, see the third figure
above).
Note: RTERM can also be
configured to be open and not
present on TMDS channels.
50 — 200 Ω
Hot plug detect specifications
HPDVH Hot plug detect high range 2.0 5.3 V
VHPDVL Hot plug detect low range 0 0.8 V
HPDZHot plug detect input impedance 10 kΩ
HPDtHot plug detect time delay 100 µs
Table 59. Electrical Characteristics (continued)
Symbol Parameter Condition Min Typ Max Unit
1ao mv — 600 "IV a v 3 g 200 mV' * m E E 200 "IV E 600 "N m "'V — 0 0 0.25 05 0.75 1.0 0.15 0.55 Normallzedhme TMDSDATAP avddtmfls — ‘lx VSMNG mm " 1w,” ..' «Inna-pusher: TMDSDATAN
Electrical Characteristics
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Figure 53. TMDS Clock Signal Definitions
Figure 54. Eye Diagram Mask Definition for HDMI Driver Signal Specification at TP1
Figure 55. Intra-Pair Skew Definition
PTMDSCLK
50%
tCPH
tCPL
prewuus much 41% 'VVIUSDATAIC‘] ‘ 07 [n —1] ~r.unsnmm H Currentcvdefnl 'rmsnmu] 7 DTIn—1] ua[n—11\n9[n—117 DDIH] ‘ b1[n] \ nun—11' lam—11 ‘bQIn—fl bDIn] bl[n] main—n V awn—n now D1[n] :5”! u ‘ Inter-punks” ta 1: 80% 50‘» 20% :9».
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Electrical Characteristics
Figure 56. Inter-Pair Skew Definition
Figure 57. TMDS Output Signals Rise and Fall Time Definition
Table 60. Switching Characteristics
Symbol Parameter Conditions Min Typ Max Unit
TMDS Drivers Specifications
Maximum serial data rate 3.4 Gbps
FTMDSCLK TMDSCLK frequency On TMDSCLKP/N outputs 25 340 MHz
PTMDSCLK TMDSCLK period RL = 50 Ω
See Figure 53.
2.94 — 40 ns
tCDC TMDSCLK duty cycle tCDC = tCPH / PTMDSCLK
RL = 50 Ω
See Figure 53.
40 50 60 %
tCPH TMDSCLK high time RL = 50 Ω
See Figure 53.
456UI
tCPL TMDSCLK low time RL = 50 Ω
See Figure 53.
456UI
TMDSCLK jitter1RL = 50 Ω — 0.25 UI
tSK(p) Intra-pair (pulse) skew RL = 50 Ω
See Figure 55.
— 0.15 UI
tSK(pp) Inter-pair skew RL = 50 Ω
See Figure 56.
——1UI
tRDifferential output signal rise
time
20–80%
RL = 50 Ω
See Figure 57.
75 0.4 UI ps
Electrical Characteristics
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4.12.9 I2C Module Timing Parameters
This section describes the timing parameters of the I2C module. Figure 58 depicts the timing of I2C
module, and Table 61 lists the I2C module timing characteristics.
Figure 58. I2C Bus Timing
tFDifferential output signal fall time 20–80%
RL = 50 Ω
See Figure 57.
75 0.4 UI ps
Differential signal overshoot Referred to 2x VSWING ——15%
Differential signal undershoot Referred to 2x VSWING ——25%
Data and Control Interface Specifications
tPower-up2HDMI 3D Tx PHY power-up time From power-down to
HSI_TX_READY assertion
— 3.35 ms
1Relative to ideal recovery clock, as specified in the HDMI specification, version 1.4a, section 4.2.3.
2For information about latencies and associated timings, see Section 4.12.7.1, “Latencies and Timing Information.”
Table 61. I2C Module Timing Parameters
ID Parameter
Standard Mode Fast Mode
Unit
Min Max Min Max
IC1 I2Cx_SCL cycle time 10 2.5 µs
IC2 Hold time (repeated) START condition 4.0 0.6 µs
IC3 Set-up time for STOP condition 4.0 0.6 µs
IC4 Data hold time 013.452010.92µs
IC5 HIGH Period of I2Cx_SCL Clock 4.0 0.6 µs
IC6 LOW Period of the I2Cx_SCL Clock 4.7 1.3 µs
IC7 Set-up time for a repeated START condition 4.7 0.6 µs
IC8 Data set-up time 250 1003—ns
Table 60. Switching Characteristics (continued)
Symbol Parameter Conditions Min Typ Max Unit
IC10 IC11 IC9
IC2 IC8 IC4 IC7 IC3
IC6
IC10
IC5
IC11 START STOP START
START
I2Cx_SDA
I2Cx_SCL
IC1
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4.12.10 Image Processing Unit (IPU) Module Parameters
The purpose of the IPU is to provide comprehensive support for the flow of data from an image sensor
and/or to a display device. This support covers all aspects of these activities:
Connectivity to relevant devicescameras, displays, graphics accelerators, and TV encoders.
Related image processing and manipulation: sensor image signal processing, display processing,
image conversions, and other related functions.
Synchronization and control capabilities, such as avoidance of tearing artifacts.
IC9 Bus free time between a STOP and START condition 4.7 1.3 µs
IC10 Rise time of both I2Cx_SDA and I2Cx_SCL signals 1000 20 + 0.1Cb4300 ns
IC11 Fall time of both I2Cx_SDA and I2Cx_SCL signals 300 20 + 0.1Cb4300 ns
IC12 Capacitive load for each bus line (Cb) 400 400 pF
1A device must internally provide a hold time of at least 300 ns for I2Cx_SDA signal to bridge the undefined region of the falling
edge of I2Cx_SCL.
2The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2Cx_SCL signal.
3A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2Cx_SCL signal.
If such a device does stretch the LOW period of the I2Cx_SCL signal, it must output the next data bit to the I2Cx_SDA line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2Cx_SCL line is released.
4Cb = total capacitance of one bus line in pF.
Table 61. I2C Module Timing Parameters (continued)
ID Parameter
Standard Mode Fast Mode
Unit
Min Max Min Max
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NXP Semiconductors 95
4.12.10.1 IPU Sensor Interface Signal Mapping
The IPU supports a number of sensor input formats. Table 62 defines the mapping of the Sensor Interface
Pins used for various supported interface formats.
Table 62. Camera Input Signal Cross Reference, Format, and Bits Per Cycle
Signal
Name1
1IPU2_CSIx stands for IPU2_CSI1 or IPU2_CSI2.
RGB565
8 bits
2 cycles
RGB5652
8 bits
3 cycles
RGB6663
8 bits
3 cycles
RGB888
8 bits
3 cycles
YCbCr4
8 bits
2 cycles
RGB5655
16 bits
1 cycle
YCbCr6
16 bits
1 cycle
YCbCr7
16 bits
1 cycle
YCbCr8
20 bits
1 cycle
IPUx_CSIx_
DATA00
———0C[0]
IPUx_CSIx_
DATA01
———0C[1]
IPUx_CSIx_
DATA02
— — — C[0] C[2]
IPUx_CSIx_
DATA03
— — — C[1] C[3]
IPUx_CSIx_
DATA04
— — — B[0] C[0] C[2] C[4]
IPU2_CSIx_
DATA_05
— — — B[1] C[1] C[3] C[5]
IPUx_CSIx_
DATA06
— — — B[2] C[2] C[4] C[6]
IPUx_CSIx_
DATA07
— — — B[3] C[3] C[5] C[7]
IPUx_CSIx_
DATA08
— — — B[4] C[4] C[6] C[8]
IPUx_CSIx_
DATA09
— — — G[0] C[5] C[7] C[9]
IPUx_CSIx_
DATA10
— — — G[1] C[6] 0 Y[0]
IPUx_CSIx_
DATA11
— — — G[2] C[7] 0 Y[1]
IPUx_CSIx_
DATA12
B[0], G[3] R[2],G[4],B[2] R/G/B[4] R/G/B[0] Y/C[0] G[3] Y[0] Y[0] Y[2]
IPUx_CSIx_
DATA13
B[1], G[4] R[3],G[5],B[3] R/G/B[5] R/G/B[1] Y/C[1] G[4] Y[1] Y[1] Y[3]
IPUx_CSIx_
DATA14
B[2], G[5] R[4],G[0],B[4] R/G/B[0] R/G/B[2] Y/C[2] G[5] Y[2] Y[2] Y[4]
IPUx_CSIx_
DATA15
B[3], R[0] R[0],G[1],B[0] R/G/B[1] R/G/B[3] Y/C[3] R[0] Y[3] Y[3] Y[5]
IPUx_CSIx_
DATA16
B[4], R[1] R[1],G[2],B[1] R/G/B[2] R/G/B[4] Y/C[4] R[1] Y[4] Y[4] Y[6]
IPUx_CSIx_
DATA17
G[0], R[2] R[2],G[3],B[2] R/G/B[3] R/G/B[5] Y/C[5] R[2] Y[5] Y[5] Y[7]
IPUx_CSIx_
DATA18
G[1], R[3] R[3],G[4],B[3] R/G/B[4] R/G/B[6] Y/C[6] R[3] Y[6] Y[6] Y[8]
IPUx_CSIx_
DATA19
G[2], R[4] R[4],G[5],B[4] R/G/B[5] R/G/B[7] Y/C[7] R[4] Y[7] Y[7] Y[9]
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4.12.10.2 Sensor Interface Timings
There are three camera timing modes supported by the IPU.
4.12.10.2.1 BT.656 and BT.1120 Video Mode
Smart camera sensors, which include imaging processing, usually support video mode transfer. They use
an embedded timing syntax to replace the IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals. The
timing syntax is defined by the BT.656/BT.1120 standards.
This operation mode follows the recommendations of ITU BT.656/ ITU BT.1120 specifications. The only
control signal used is IPU2_CSIx_PIX_CLK. Start-of-frame and active-line signals are embedded in the
data stream. An active line starts with a SAV code and ends with a EAV code. In some cases, digital
blanking is inserted in between EAV and SAV code. The CSI decodes and filters out the timing-coding
from the data stream, thus recovering IPU2_CSIx_VSYNC and IPU2_CSIx_HSYNC signals for internal
use. On BT.656 one component per cycle is received over the IPU2_CSIx_DATA_EN bus. On BT.1120
two components per cycle are received over the IPU2_CSIx_DATA_EN bus.
4.12.10.2.2 Gated Clock Mode
The IPU2_CSIx_VSYNC, IPU2_CSIx_HSYNC, and IPU2_CSIx_PIX_CLK signals are used in this
mode. See Figure 59.
Figure 59. Gated Clock Mode Timing Diagram
A frame starts with a rising edge on IPU2_CSIx_VSYNC (all the timings correspond to straight polarity
of the corresponding signals). Then IPU2_CSIx_HSYNC goes to high and hold for the entire line. Pixel
clock is valid as long as IPU2_CSIx_HSYNC is high. Data is latched at the rising edge of the valid pixel
clocks. IPU2_CSIx_HSYNC goes to low at the end of line. Pixel clocks then become invalid and the CSI
2The MSB bits are duplicated on LSB bits implementing color extension.
3The two MSB bits are duplicated on LSB bits implementing color extension.
4YCbCr, 8 bits—Supported within the BT.656 protocol (sync embedded within the data stream).
5RGB, 16 bits—Supported in two ways: (1) As a “generic data” input—with no on-the-fly processing; (2) With on-the-fly
processing, but only under some restrictions on the control protocol.
6YCbCr, 16 bits—Supported as a “generic-data” input—with no on-the-fly processing.
7YCbCr, 16 bits—Supported as a sub-case of the YCbCr, 20 bits, under the same conditions (BT.1120 protocol).
8YCbCr, 20 bits—Supported only within the BT.1120 protocol (syncs embedded within the data stream).
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Electrical Characteristics
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NXP Semiconductors 97
stops receiving data from the stream. For the next line, the IPU2_CSIx_HSYNC timing repeats. For the
next frame, the IPU2_CSIx_VSYNC timing repeats.
4.12.10.2.3 Non-Gated Clock Mode
The timing is the same as the gated-clock mode (described in Section 4.12.10.2.2, “Gated Clock Mode,”)
except for the IPU2_CSIx_HSYNC signal, which is not used (see Figure 60). All incoming pixel clocks
are valid and cause data to be latched into the input FIFO. The IPU2_CSIx_PIX_CLK signal is inactive
(states low) until valid data is going to be transmitted over the bus.
Figure 60. Non-Gated Clock Mode Timing Diagram
The timing described in Figure 60 is that of a typical sensor. Some other sensors may have a slightly
different timing. The CSI can be programmed to support rising/falling-edge triggered
IPU2_CSIx_VSYNC; active-high/low IPU2_CSIx_HSYNC; and rising/falling-edge triggered
IPU2_CSIx_PIX_CLK.
IPU2_CSIx_VSYNC
IPU2_CSIx_PIX_CLK
IPU2_CSIx_DATA_EN[19:0] invalid
1st byte
n+1th frame
invalid
1st byte
nth frame
Start of Frame
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98 NXP Semiconductors
Electrical Characteristics
4.12.10.3 Electrical Characteristics
Figure 61 depicts the sensor interface timing. IPU2_CSIx_PIX_CLK signal described here is not
generated by the IPU. Table 63 lists the sensor interface timing characteristics.
Figure 61. Sensor Interface Timing Diagram
4.12.10.4 IPU Display Interface Signal Mapping
The IPU supports a number of display output video formats. Table 64 defines the mapping of the Display
Interface Pins used during various supported video interface formats.
Table 63. Sensor Interface Timing Characteristics
ID Parameter Symbol Min Max Unit
IP1 Sensor output (pixel) clock frequency Fpck 0.01 180 MHz
IP2 Data and control setup time Tsu 2 ns
IP3 Data and control holdup time Thd 1 ns
Vsync to Hsync Tv-h 1/Fpck ns
Vsync and Hsync pulse width Tpulse 1/Fpck ns
Vsync to first data Tv-d 1/Fpck ns
Table 64. Video Signal Cross-Reference
i.MX
6DualPlus/6QuadPlus LCD
Comment1,2
Port Name
(x = 0, 1)
RGB,
Signal
Name
(General)
RGB/TV Signal Allocation (Example)
16-bit
RGB
18-bit
RGB
24 Bit
RGB
8-bit
YCrCb3
16-bit
YCrCb
20-bit
YCrCb
IPUx_DISPx_DAT00 DAT[0] B[0] B[0] B[0] Y/C[0] C[0] C[0]
IPUx_DISPx_DAT01 DAT[1] B[1] B[1] B[1] Y/C[1] C[1] C[1]
IPUx_DISPx_DAT02 DAT[2] B[2] B[2] B[2] Y/C[2] C[2] C[2]
IPUx_DISPx_DAT03 DAT[3] B[3] B[3] B[3] Y/C[3] C[3] C[3]
IPUx_DISPx_DAT04 DAT[4] B[4] B[4] B[4] Y/C[4] C[4] C[4]
IP3
IPUx_CSIx_DATA_EN,
IPUx_CSIx_VSYNC,
IP2 1/IP1
IPUx_CSIx_PIX_CLK
(Sensor Output)
IPUx_CSIx_HSYNC
Electrical Characteristics
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NXP Semiconductors 99
IPUx_DISPx_DAT05 DAT[5] G[0] B[5] B[5] Y/C[5] C[5] C[5]
IPUx_DISPx_DAT06 DAT[6] G[1] G[0] B[6] Y/C[6] C[6] C[6]
IPUx_DISPx_DAT07 DAT[7] G[2] G[1] B[7] Y/C[7] C[7] C[7]
IPUx_DISPx_DAT08 DAT[8] G[3] G[2] G[0] Y[0] C[8]
IPUx_DISPx_DAT09 DAT[9] G[4] G[3] G[1] Y[1] C[9]
IPUx_DISPx_DAT10 DAT[10] G[5] G[4] G[2] Y[2] Y[0]
IPUx_DISPx_DAT11 DAT[11] R[0] G[5] G[3] Y[3] Y[1]
IPUx_DISPx_DAT12 DAT[12] R[1] R[0] G[4] Y[4] Y[2]
IPUx_DISPx_DAT13 DAT[13] R[2] R[1] G[5] Y[5] Y[3]
IPUx_DISPx_DAT14 DAT[14] R[3] R[2] G[6] Y[6] Y[4]
IPUx_DISPx_DAT15 DAT[15] R[4] R[3] G[7] Y[7] Y[5]
IPUx_DISPx_DAT16 DAT[16] R[4] R[0] Y[6]
IPUx_DISPx_DAT17 DAT[17] R[5] R[1] Y[7]
IPUx_DISPx_DAT18 DAT[18] — R[2] Y[8]
IPUx_DISPx_DAT19 DAT[19] — R[3] Y[9]
IPUx_DISPx_DAT20 DAT[20] — R[4]
IPUx_DISPx_DAT21 DAT[21] — R[5]
IPUx_DISPx_DAT22 DAT[22] — R[6]
IPUx_DISPx_DAT23 DAT[23] — R[7]
IPUx_DIx_DISP_CLK PixCLK
IPUx_DIx_PIN01 May be required for anti-tearing
IPUx_DIx_PIN02 HSYNC
IPUx_DIx_PIN03 VSYNC VSYNC out
Table 64. Video Signal Cross-Reference (continued)
i.MX
6DualPlus/6QuadPlus LCD
Comment1,2
Port Name
(x = 0, 1)
RGB,
Signal
Name
(General)
RGB/TV Signal Allocation (Example)
16-bit
RGB
18-bit
RGB
24 Bit
RGB
8-bit
YCrCb3
16-bit
YCrCb
20-bit
YCrCb
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NOTE
Table 64 provides information for both the DISP0 and DISP1 ports.
However, DISP1 port has reduced pinout depending on IOMUXC
configuration and therefore may not support all configurations. See the
IOMUXC table for details.
4.12.10.5 IPU Display Interface Timing
The IPU Display Interface supports two kinds of display accesses: synchronous and asynchronous. There
are two groups of external interface pins to provide synchronous and asynchronous controls.
4.12.10.5.1 Synchronous Controls
The synchronous control changes its value as a function of a system or of an external clock. This control
has a permanent period and a permanent waveform.
IPUx_DIx_PIN04 Additional frame/row synchronous
signals with programmable timing
IPUx_DIx_PIN05 —
IPUx_DIx_PIN06 —
IPUx_DIx_PIN07 —
IPUx_DIx_PIN08 —
IPUx_DIx_D0_CS —
IPUx_DIx_D1_CS Alternate mode of PWM output for
contrast or brightness control
IPUx_DIx_PIN11 —
IPUx_DIx_PIN12 —
IPUx_DIx_PIN13 Register select signal
IPUx_DIx_PIN14 Optional RS2
IPUx_DIx_PIN15 DRDY/DV Data validation/blank, data enable
IPUx_DIx_PIN16 Additional data synchronous
signals with programmable
features/timing
IPUx_DIx_PIN17 Q
1 Signal mapping (both data and control/synchronization) is flexible. The table provides examples.
2 Restrictions for ports IPUx_DISPx_DAT00 through IPUx_DISPx_DAT23 are as follows:
A maximum of three continuous groups of bits can be independently mapped to the external bus. Groups must not overlap.
The bit order is expressed in each of the bit groups, for example, B[0] = least significant blue pixel bit.
3This mode works in compliance with recommendation ITU-R BT.656. The timing reference signals (frame start, frame end, line
start, and line end) are embedded in the 8-bit data bus. Only video data is supported, transmission of non-video related data
during blanking intervals is not supported.
Table 64. Video Signal Cross-Reference (continued)
i.MX
6DualPlus/6QuadPlus LCD
Comment1,2
Port Name
(x = 0, 1)
RGB,
Signal
Name
(General)
RGB/TV Signal Allocation (Example)
16-bit
RGB
18-bit
RGB
24 Bit
RGB
8-bit
YCrCb3
16-bit
YCrCb
20-bit
YCrCb
Electrical Characteristics
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NXP Semiconductors 101
There are special physical outputs to provide synchronous controls:
The ipp_disp_clk is a dedicated base synchronous signal that is used to generate a base display
(component, pixel) clock for a display.
The ipp_pin_1– ipp_pin_7 are general purpose synchronous pins, that can be used to provide
HSYNC, VSYNC, DRDY or any else independent signal to a display.
The IPU has a system of internal binding counters for internal events (such as, HSYNC/VSYNC)
calculation. The internal event (local start point) is synchronized with internal DI_CLK. A suitable control
starts from the local start point with predefined UP and DOWN values to calculate control’s changing
points with half DI_CLK resolution. A full description of the counter system can be found in the IPU
chapter of the i.MX 6DualPlus/6QuadPlus reference manual (IMX6DQPRM).
4.12.10.5.2 Asynchronous Controls
The asynchronous control is a data-oriented signal that changes its value with an output data according to
additional internal flags coming with the data.
There are special physical outputs to provide asynchronous controls, as follows:
The ipp_d0_cs and ipp_d1_cs pins are dedicated to provide chip select signals to two displays.
The ipp_pin_11– ipp_pin_17 are general purpose asynchronous pins, that can be used to provide
WR. RD, RS or any other data-oriented signal to display.
NOTE
The IPU has independent signal generators for asynchronous signals
toggling. When a DI decides to put a new asynchronous data on the bus, a
new internal start (local start point) is generated. The signal generators
calculate predefined UP and DOWN values to change pins states with half
DI_CLK resolution.
4.12.10.6 Synchronous Interfaces to Standard Active Matrix TFT LCD Panels
4.12.10.6.1 IPU Display Operating Signals
The IPU uses four control signals and data to operate a standard synchronous interface:
IPP_DISP_CLK—Clock to display
HSYNC—Horizontal synchronization
VSYNC—Vertical synchronization
DRDY—Active data
All synchronous display controls are generated on the base of an internally generated “local start point”.
The synchronous display controls can be placed on time axis with DI’s offset, up and down parameters.
The display access can be whole number of DI clock (Tdiclk) only. The IPP_DATA can not be moved
relative to the local start point. The data bus of the synchronous interface is output direction only.
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Electrical Characteristics
4.12.10.6.2 LCD Interface Functional Description
Figure 62 depicts the LCD interface timing for a generic active matrix color TFT panel. In this figure,
signals are shown with negative polarity. The sequence of events for active matrix interface timing is:
DI_CLK internal DI clock is used for calculation of other controls.
IPP_DISP_CLK latches data into the panel on its negative edge (when positive polarity is selected).
In active mode, IPP_DISP_CLK runs continuously.
HSYNC causes the panel to start a new line. (Usually IPUx_DIx_PIN02 is used as HSYNC.)
VSYNC causes the panel to start a new frame. It always encompasses at least one HSYNC pulse.
(Usually IPUx_DIx_PIN03 is used as VSYNC.)
DRDY acts like an output enable signal to the CRT display. This output enables the data to be
shifted onto the display. When disabled, the data is invalid and the trace is off.
(DRDY can be used either synchronous or asynchronous generic purpose pin as well.)
Figure 62. Interface Timing Diagram for TFT (Active Matrix) Panels
4.12.10.6.3 TFT Panel Sync Pulse Timing Diagrams
Figure 63 depicts the horizontal timing (timing of one line), including both the horizontal sync pulse and
the data. All the parameters shown in the figure are programmable. All controls are started by
corresponding internal events—local start points. The timing diagrams correspond to inverse polarity of
the IPP_DISP_CLK signal and active-low polarity of the HSYNC, VSYNC, and DRDY signals.
123 mm–1
HSYNC
VSYNC
HSYNC
LINE 1 LINE 2 LINE 3 LINE 4 LINE n-1 LINE n
DRDY
IPP_DISP_CLK
IPP_DATA
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Electrical Characteristics
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NXP Semiconductors 103
Figure 63. TFT Panels Timing Diagram—Horizontal Sync Pulse
Figure 64 depicts the vertical timing (timing of one frame). All parameters shown in the figure are
programmable.
Figure 64. TFT Panels Timing Diagram—Vertical Sync Pulse
DI clock
VSYNC
HSYNC
DRDY
D0 D1
IP5o
IP13o
IP9o
IP8o IP8
IP9
Dn
IP10
IP7
IP5
IP6
local start point
local start point
local start point
IPP_DISP_CLK
IPP_DATA