ADXL356/ADXL357 Data Sheet
Rev. 0 | Page 22 of 42
AXES OF ACCELERATION SENSITIVITY
Figure 60 shows the axes of acceleration sensitivity. Note that
the output voltage increases when accelerated along the
Figure 60. Axes of Acceleration Sensitivity
There are two methods for applying power to the device.
Typically, internal LDO regulators generate the 1.8 V power for
the analog and digital supplies, V1P8ANA and V1P8DIG, respectively.
Optionally, connecting VSUPPLY to VSS and driving V1P8ANA and
V1P8DIG with an external supply can supply V1P8ANA and V1P8DIG.
When using the internal LDO regulators, connect VSUPPLY to a
voltage source between 2.25 V to 3.6 V. In this case, VDDIO and
VSUPPLY can be powered in parallel. VSUPPLY must not exceed the
VDDIO voltage by greater than 0.5 V. If necessary, VDDIO can be
powered before VSUPPLY.
When disabling the internal LDO regulators and using an external
1.8 V supply to power V1P8ANA and V1P8DIG, tie VSUPPLY to ground,
and set V1P8ANA and V1P8DIG to the same final voltage level. In the
case of bypassing the LDOs, the recommended power sequence is
to apply power to VDDIO, followed by V1P8DIG approximately 10 µs
later, and then V1P8ANA approximately 10 µs later. If necessary,
V1P8DIG and VDDIO can be powered from the same 1.8 V supply,
which can also be tied to V1P8ANA with proper isolation. In this
case, proper decoupling and low frequency isolation is important
to maintain the noise performance of the sensor.
POWER SUPPLY DESCRIPTION
The ADXL356/ADXL357 have four different power supply
domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal
analog and digital circuitry operates at 1.8 V nominal.
VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two
LDO regulators that generate the nominal 1.8 V outputs for
V1P8ANA and V1P8DIG. Connect VSUP PLY to VSS to disable the LDO
regulators, which allows driving V1P8ANA and V1P8DIG from an
All sensor and analog signal processing circuitry operates in
this domain. Offset and sensitivity of the analog output
ADXL356 are ratiometric to this supply voltage. When using
external ADCs, use V1P8ANA as the reference voltage. The digital
output ADXL357 includes ADCs that are ratiometric to V1P8ANA,
thereby rendering offset and sensitivity insensitive to the value
of V1P8ANA. V1P8ANA can be an input or an output as defined by the
state of the VSUPPLY voltage.
V1P8DIG is the supply voltage for the internal logic circuitry. A
separate LDO regulator decouples the digital supply noise from
the analog signal path. V1P8ANA can be an input or an output as
defined by the state of the VSUPPLY voltage. If driven externally,
V1P8DIG must be the same voltage as the V1P8ANA voltage.
The VDDIO value determines the logic high levels. On the analog
output ADXL356, VDDIO sets the logic high level for the self test
pins, ST1 and ST2, as well as the STBY pin. On the digital output
ADXL357, VDDIO sets the logic high level for communications
interface ports, as well as the interrupt and DRDY outputs.
The LDO regulators are operational when VSUPPLY is between
2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs in
this mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA and
V1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range.
To avoid electrostatic capture of the proof mass when the
accelerometer is subject to input acceleration beyond its full-
scale range, all sensor drive clocks turn off for 0.5 ms. In the
±10 g/±10.24 g range setting, the overrange protection activates
for input signals beyond approximately ±40 g (±25%), and for
the ±20 g/±20.48 g and ±40 g/±40.95 g range settings, the
threshold corresponds to about ±80 g (±25%).
When overrange protection occurs, the XOUT, YOUT, and ZOUT pins
on the ADXL356 begin to drive to midscale. The ADXL357
floats toward zero, and first in, first out (FIFO) buffer begins
filling with this data.
The ADXL356 and ADXL357 incorporate a self test feature
that effectively tests the mechanical and electronic system.
Enabling self test stimulates the sensor electrostatically to
produce an output corresponding to the test signal applied as
well as the mechanical force exerted. Only the z-axis response is
specified to validate device functionality.
In the ADXL356, drive the ST1 pin to VDDIO to invoke self test
mode. Then, by driving the ST2 pin to VDDIO, the ADXL356
applies an electrostatic force to the mechanical sensor and
induces a change in output in response to the force. The self test
delta (or response) is the difference in output voltage in the
z-axis when ST2 is high vs. ST2 is low, while ST1 is asserted.
After the self test measurement is complete, bring both pins low
to resume normal operation.
The self test operation is similar in the ADXL357, except ST1
and ST2 can be accessed through the SELF_TEST register